5.5.21 · D3Embedded Systems & Real-Time Software

Worked examples — Hardware-in-the-Loop (HIL) simulation — real hardware, simulated plant

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This page is a practice arena. The parent note built the theory (real ECU, simulated plant, real-time deadline, the motor update equations). Here we grind through every kind of situation a HIL problem can throw at you — normal numbers, zero inputs, degenerate cases, timing that just barely fails, and the exam twists that catch people.

Before we start, one reminder in plain words: in HIL, a real controller (the ECU — the little computer that would sit inside a real car) is fooled into thinking it talks to real motors and sensors. In truth it talks to a simulator — a second computer solving physics equations fast enough to answer before the ECU asks again. Every example below lives inside that loop.

Figure — Hardware-in-the-Loop (HIL) simulation — real hardware, simulated plant

The picture above is the loop every example freezes one moment of: the ECU emits a command, the I/O box carries it to the simulator, the simulator does its physics, the I/O box carries a sensor value back. Keep it in mind — each example is one arrow on this ring.


The scenario matrix

Every HIL problem you will meet falls into one of these case classes. The map below arranges them; each numbered example is tagged with the cell it covers, so by the end you have touched every box.

Figure — Hardware-in-the-Loop (HIL) simulation — real hardware, simulated plant
Case class What makes it tricky Covered by
A. Normal closed loop ordinary numbers, everything in range Ex 1
B. Real-time deadline PASS compute time comfortably under the step Ex 2
C. Real-time deadline FAIL simulator too slow → loop breaks Ex 3
D. Zero / degenerate input duty cycle , or at start Ex 4
E. Sign / direction flip negative torque, motor spinning backward Ex 5
F. Signal-conversion limits (clip, both rails) sensor voltage hits or ; current hits Ex 6
G. Real-world word problem full idle-speed scenario, settling time Ex 7
H. Exam-style twist "why does SIL miss this but HIL catches it?" Ex 8
I. Limiting / steady-state , what speed does it settle at? Ex 9

We reuse one DC-motor plant for the numeric cases so the numbers stay comparable. Its constants (all invented but consistent):

These plug into the quasi-static update chain from the parent note (the inductance term dropped, as defined above):


Example 1 — Normal closed loop [Case A]

Forecast: guess first — will the speed go up, down, or stay put? (Hint: is the motor being pushed harder than the back-EMF resists?)

  1. Voltage from PWM. . Why this step? The PWM duty cycle is the only thing the ECU physically hands the simulator; everything downstream flows from it.

  2. Current. . Why this step? Voltage minus back-EMF is the net push across the resistance; Ohm's law turns it into current. (, so no clamp needed here.)

  3. Torque. . Why this step? Current makes torque — this is the Lorentz-force link that actually spins the shaft.

  4. New speed (Euler). . Why this step? Newton's law says net torque over inertia is angular acceleration; Euler multiplies that by the time step to advance one tick.

Verify: net torque is positive, so speed rises — matches the forecast that overpowers the back-EMF. Units: ✓ (since ). New speed .


Example 2 — Deadline PASS [Case B]

Forecast: add the two times, compare to the step. Pass or fail?

Figure — Hardware-in-the-Loop (HIL) simulation — real hardware, simulated plant
  1. Total compute. . Why this step? The deadline covers everything between receiving the ECU command and delivering the sensor answer — compute and I/O.

  2. Available budget. . Why this step? The ECU asks again every ; the answer must be ready before then.

  3. Compare and take utilisation. . Slack . Why this step? The real-time law from the parent note is ; utilisation just re-expresses it as "what fraction of the tick did we burn?" — is well under .

Verify: utilisation means headroom, so no time dilation — the ECU never notices it is in a simulation. PASS.


Example 3 — Deadline FAIL [Case C]

Forecast: total vs. budget again — but this time think about what the ECU experiences.

  1. Total. . Why this step? Same accounting; the fault will show in the sum.

  2. Compare. . Overrun , utilisation . Why this step? Crossing utilisation is the definition of a missed hard deadline.

  3. Consequence. The simulator delivers last-tick sensor values late. The ECU reads stale encoder counts, computes control on old data, and the closed loop can go unstable (the "time dilation" warned about in the parent note). Why this step? HIL only stays honest while the simulation keeps up; once it lags, results are meaningless.

Verify: confirms overrun; the deficit means we must either speed the solver (fixed-step, lookup tables, FPGA) or slow the loop. See FPGA for Real-Time Simulation and Real-time Operating Systems (RTOS) for the fixes. FAIL.


Example 4 — Zero / degenerate input [Case D]

Forecast: with zero volts and zero speed, does anything move?

  1. Voltage. . Why this step? Duty cycle zero means the PWM is fully off — no drive at all.

  2. Current. . Why this step? We divide by , not by anything that could be zero — so the formula stays safe even at rest. This is the degenerate check.

  3. Torque & speed. ; . Why this step? No current → no torque → no change; the motor correctly stays still.

Verify: all zeros, no division by zero (the only denominator is , a fixed constant), speed unchanged at . A HIL rig that produced garbage here would fail the boot-sequence test in Example 7's step 1. Clean.


Example 5 — Sign / direction flip [Case E]

Forecast: compare drive voltage to back-EMF. Which is bigger?

  1. Voltage. . Why this step? Sets the drive side of the tug-of-war.

  2. Back-EMF. . Why this step? A spinning motor generates its own voltage opposing the supply; here it is larger than the supply.

  3. Current (goes negative). . Why this step? The sign flips — current now flows backward, meaning the motor acts as a generator (braking). A HIL model must handle this sign, or braking scenarios test wrong. (, no clamp.)

  4. New speed. ; . Why this step? Negative torque plus damping decelerates — the motor slows, as physics demands.

Verify: speed dropped from to ; current sign is negative → regenerative braking captured correctly. Sanity: back-EMF () drive () ⇒ braking ✓.


Example 6 — Signal & current limits: both rails and the current ceiling [Case F]

Forecast: the linear encoding is happy to go below and above — but the hardware is not. Guess which of the three temperatures get clipped, and whether the stall current blows past .

Part (a): both rails.

  1. Hot — upper rail. . ECU decodes . Why this step? The DAC saturates at its top rail; above every temperature reads the same — a high-side blind spot.

  2. Cold — lower rail. . ECU decodes . Why this step? A DAC cannot output negative volts on a pin, so it floors at — the ECU thinks it is when the plant is really . This lower-rail case is just as real as the upper one and equally invisible to the ECU.

  3. In range — no clip. , inside , so and decodes back exactly. Why this step? Shows the encoding is faithful only inside the rail window; the fix is to rescale so the whole to span maps into .

Part (b): current ceiling.

  1. Raw stall current. , . Why this step? At standstill there is no back-EMF, so the full supply drives current — this is the worst case that stresses the winding.

  2. Clamp to the ceiling. , so a faithful model outputs , giving . Why this step? Real drivers current-limit; if the HIL model let through it would over-predict torque and miss the ECU's over-current protection logic (a Fault Injection Testing target).

Verify (a): hot reads (rail ) ✓; cold reads (rail ) ✓; in-range decodes exactly ✓ — both rails and the clean middle all shown. Verify (b): clamps to , ; without the clamp torque would be , a over-estimate.


Example 7 — Real-world word problem: idle-speed test [Case G]

Forecast: eyeball the sequence — does the distance from 800 shrink, or grow?

Figure — Hardware-in-the-Loop (HIL) simulation — real hardware, simulated plant
  1. PASS band. . Why this step? The test's acceptance criterion is a fixed window; the last value must land inside it.

  2. Check last value. ✓ → PASS on the final reading. Why this step? That is literally the PASS criterion from the parent's Example 1.

  3. Damping = error about the setpoint shrinks. The correct measure of settling is the error , i.e. how far each sample sits from the target, not the step-to-step jump. Compute: , , , . After the first cranking transient the errors fall — a shrinking magnitude that straddles from both sides. That decaying, alternating-sign error is the textbook signature of a damped (stable, settling) oscillation. Why this step? The parent warned that a growing swing means too high. The proper test is whether the error envelope decays; here it does, so the PID gains are healthy.

  4. Unit conversion. . Why this step? Our plant equations use ; converting lets the idle target feed the motor model directly.

Verify: last value inside ✓; setpoint errors after the transient are decreasing ✓ (damped); (check: ✓). See PID Control for the tuning behind this response.


Example 8 — Exam-style twist [Case H]

Forecast: the bug is about real timing on real silicon, inside a live loop. Ask two yes/no questions of each level — does it run real hardware? does it close a real-time loop? — and let the answers rank them.

  1. MIL — miss it. The controller is still just a block-diagram model running on your PC; there is no code, no processor, no ISR. The lateness has nowhere to happen. Why this step? You cannot reproduce a hardware-timing bug on something that contains zero hardware.

  2. SIL — miss it. Now the actual C code compiles and runs, but on the PC, not the target chip. PC timing has no relation to the microcontroller's ISR latency, so again the bug never fires. Why this step? SIL checks logic, not real interrupt timing — the very thing this bug depends on.

  3. PIL — partially. The code runs on the real processor, so the ISR and its lateness now genuinely occur and can corrupt the variable. But the plant is still numbers fed in from the PC, not a live real-time closed loop, so you may see the corruption without seeing its full physical consequence. Why this step? PIL adds real silicon (catches the cause) but not real-time signals (may not show the effect).

  4. HIL — catches it fully. Real ECU and a live closed loop: the ISR fires late on the genuine microcontroller, corrupts the shared variable, the ECU emits a wrong actuator command, the real-time plant simulator reacts to that wrong command and feeds altered sensor values back — so the fault shows up as visibly wrong closed-loop behaviour (e.g. a speed glitch on the log). Why this step? HIL is the first level with both real hardware timing and a live physical loop — exactly the two ingredients this bug needs to become an observable failure.

Verify: detection strength ranks HIL PIL SIL MIL for a hardware-timing bug. Two boolean tests decide it — "real chip?" (false, false, true, true) and "live real-time loop?" (false, false, false, true) — and HIL is the only level that scores true on both. This matches the parent note's promise that HIL "eliminates works in simulation but fails in hardware surprises." Closure: the further right you push a test toward real hardware plus real signals, the more timing-and-integration faults it can expose — which is precisely why HIL exists. (Add a real vehicle around it and you reach Vehicle-in-the-Loop (VIL).)


Example 9 — Limiting / steady state [Case I]

Forecast: at steady state, acceleration is zero — so what must the net torque be?

  1. Set acceleration to zero. Steady state means , so the bracket in the update must vanish: . Why this step? The whole point of a limit: the Euler increment vanishes, leaving an algebra equation, no more stepping.

  2. Expand torque in terms of . With and : Why this step? We want one equation in the single unknown .

  3. Solve for . Why this step? Rearranging isolates the steady speed; plugging the shared constants gives the number the HIL log should asymptote to.

Verify: at : back-EMF , current (well under ), torque , damping torque — equal, so net torque ✓. Steady state , and note it sits above Example 1's one-step , confirming the motor is still accelerating there.


Recall Quick self-test

One-step new speed at (Ex 1)? ::: Utilisation when compute, step (Ex 2)? ::: , PASS Overrun when compute, step (Ex 3)? ::: , FAIL Current sign when back-EMF (V) beats drive (V) (Ex 5)? ::: negative, (braking) Cold encoded on a V pin reads what (Ex 6)? ::: (floored at the lower rail) Stall current at before/after clamp (Ex 6)? ::: raw → clamped to Steady-state speed at (Ex 9)? :::


Connections: the plant math here comes from the parent HIL note; the timing budget links to Real-time Operating Systems (RTOS) and FPGA for Real-Time Simulation; the idle-speed loop uses PID Control and PWM (Pulse Width Modulation); the temperature/current failure cases connect to Fault Injection Testing and the sensor frames to CAN Bus Protocol; the test-level ranking touches Model-in-the-Loop (MIL), Software-in-the-Loop (SIL), Processor-in-the-Loop (PIL) and Vehicle-in-the-Loop (VIL).