Exercises — Hardware-in-the-Loop (HIL) simulation — real hardware, simulated plant
Notation we will reuse (defined once, here)
Before any problem, let us earn every symbol so nothing surprises you later.
L1 — Recognition
Exercise 1.1 (L1)
Which of these is the defining feature of HIL that separates it from Software-in-the-Loop (SIL)? (a) The plant is simulated. (b) The controller runs on the real target hardware. (c) A PID loop is used. (d) The test is automated.
Recall Solution
(b). In both SIL and HIL the plant is simulated (so (a) is true of both — not a distinguishing feature). PID and automation appear in many test styles. The unique HIL signature is that the production ECU/microcontroller executes real firmware, exchanging real electrical signals. Compare the ladder: Model-in-the-Loop (MIL) (all model), Software-in-the-Loop (SIL) (code on PC), Processor-in-the-Loop (PIL) (code on target CPU, no real I/O), then HIL (target + real I/O).
Exercise 1.2 (L1)
A HIL simulator runs at . What is its time step in milliseconds?
Recall Solution
L2 — Application
Exercise 2.1 (L2)
ECU commands duty cycle into a motor on a battery. What voltage does the HIL plant model apply?
Recall Solution
Why: PWM's average delivered voltage is duty cycle times supply — this is exactly the first step the simulator does when it reads the ECU's PWM pin.
Exercise 2.2 (L2)
Continuing: motor resistance , back-EMF constant , current shaft speed . Using the quasi-static current equation , find the current .
Recall Solution
Why quasi-static: we dropped the inductance term because it is tiny compared to , which lets the simulator finish inside .
Exercise 2.3 (L2)
Torque constant . What motor torque does that current produce?
Recall Solution
L3 — Analysis
Exercise 3.1 (L3)
Take the torque from above. Load torque , damping , inertia , current , step . Do one Euler update to find .
Recall Solution — walk the figure
The Euler update from the parent note: Net torque: Acceleration step: What it looks like: in the figure the shaft speed nudges up by a hair because net torque is positive — the tiny slope segment over one .
Exercise 3.2 (L3)
Convert both and the updated to RPM.
Recall Solution
Exercise 3.3 (L3)
A step took at . What fraction of the budget is used, and is the rig real-time-valid?
Recall Solution
Since , the law holds — valid, but with only headroom. Cutting it close: a slower branch (e.g. a fault-injection path) could blow the deadline. See Real-time Operating Systems (RTOS).
L4 — Synthesis
Exercise 4.1 (L4)
An engine-idle HIL test must run the plant at . Three tasks run each step: combustion model , crankshaft dynamics , and I/O generation (encoder pulses + CAN Bus Protocol frames) . (a) Total compute? (b) Is it valid? (c) What is the maximum update rate this workload could sustain?
Recall Solution
(a) Total: (b) → valid, headroom (). (c) The fastest step you can sustain has , so Above that, compute overruns the step and the ECU sees frozen sensors.
Exercise 4.2 (L4)
Sketch (in words + reference the figure) a fault-injection test plan that verifies the ECU limps safely when a throttle-position sensor reads open-circuit. List the closed-loop cycle and the PASS criterion.
Recall Solution — see the loop figure
Plan (this is Fault Injection Testing layered on HIL):
- Bring engine to steady idle in the plant model.
- Inject fault: command the I/O box's DAC to drive the TPS line to (or float it) — simulating a broken sensor wire.
- ECU's diagnostic reads an implausible/out-of-range TPS.
- ECU should set a fault code and enter limp-home (fixed safe throttle map).
- Plant responds; measure engine speed and the throttle-motor PWM. PASS criterion: within of injection the ECU (a) raises the diagnostic flag and (b) keeps engine speed within a safe band (no stall, no runaway). The figure shows the closed loop with the red fault-injection tap cutting into the sensor path. Why HIL and not SIL here: the fault lives in the electrical signal path (open circuit, wrong voltage). Only real I/O hardware can reproduce that; a pure-software Software-in-the-Loop (SIL) rig cannot break a wire.
L5 — Mastery
Exercise 5.1 (L5)
Full idle-control loop. Start: . Motor params: , , , , , , . A PID Control loop with only proportional term drives duty cycle from speed error toward a setpoint : Compute the first two Euler steps: give , , , at each. (Use quasi-static current, clip negative current to .)
Recall Solution — step by step
Step k = 0 ():
- Error . (saturated).
- .
- .
- .
- .
- .
Step k = 1 ():
- Error . (still saturated).
- .
- .
- .
- .
- .
Reading it: at start the error is huge, so the P-controller slams the duty cycle to its ceiling (, saturated). The shaft crawls up from rest — realistic, because inertia resists sudden speed. Only much later (as ) will come off the rail and the loop settle.
Exercise 5.2 (L5)
Mastery synthesis question (concept + arithmetic): You must add a stiff electrical sub-model (fast dynamics) whose stability demands , but your current mechanical loop is happy at . Each electrical step costs of compute; the mechanical step costs but only needs to run every . (a) If everything ran at the fast rate, what is the worst-case compute per slice on the slice that also does mechanics, and is it valid? (b) Name the architectural fix and one hardware option.
Recall Solution
(a) On the unlucky slice both run: , but the slice budget is only . Since , it overruns by — invalid. Even the electrical-only slices are fine (); the mechanical burst is what kills it. (b) Multi-rate / multi-tasking simulation: run the electrical model in a fast task and the mechanical model in a slower task, on separate cores or a hard-real-time scheduler (Real-time Operating Systems (RTOS)), so the heavy mechanical work never lands inside a single fast slice. Hardware option: offload the stiff, deterministic electrical ODE to an FPGA for Real-Time Simulation running in parallel at sub-microsecond rates, freeing the CPU. That is exactly why FPGAs appear in high-end HIL rigs.
Recall Self-test — one-line recalls
HIL's defining feature vs SIL ::: the controller runs on the real target hardware with real I/O The real-time validity law ::: Max sustainable update rate ::: Convert rad/s to RPM ::: multiply by Fix for a stiff fast sub-model that overruns ::: multi-rate scheduling and/or an FPGA co-processor Why back-EMF must be subtracted ::: current feels only leftover voltage