5.5.21 · D3 · HinglishEmbedded Systems & Real-Time Software

Worked examplesHardware-in-the-Loop (HIL) simulation — real hardware, simulated plant

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5.5.21 · D3 · Coding › Embedded Systems & Real-Time Software › Hardware-in-the-Loop (HIL) simulation — real hardware, simul

Yeh page ek practice arena hai. Parent note ne theory build ki (real ECU, simulated plant, real-time deadline, motor update equations). Yahan hum har tarah ki situation ke through grind karte hain jo ek HIL problem throw kar sakta hai — normal numbers, zero inputs, degenerate cases, timing jo barely fail hoti hai, aur exam ke woh twists jo logon ko pakad lete hain.

Shuru karne se pehle, ek reminder plain words mein: HIL mein, ek real controller (ECU — woh chota sa computer jo ek real car ke andar hota) ko fool kiya jaata hai ki woh real motors aur sensors se baat kar raha hai. Sachchi baat mein woh ek simulator se baat karta hai — ek doosra computer jo physics equations ko itni tez solve karta hai ki ECU ke dobara poochne se pehle jawab de sake. Neeche ke har example is hi loop ke andar rehte hain.

Figure — Hardware-in-the-Loop (HIL) simulation — real hardware, simulated plant

Upar ki picture woh loop hai jise har example ek moment par freeze karta hai: ECU ek command emit karta hai, I/O box use simulator tak le jaata hai, simulator apni physics karta hai, I/O box ek sensor value wapas le jaata hai. Ise yaad rakho — har example is ring ka ek arrow hai.


Scenario matrix

Har HIL problem jo tumhe milegi woh in case classes mein se ek mein fit hogi. Neeche ka map unhe arrange karta hai; har numbered example us cell ke saath tagged hai jo woh cover karta hai, toh end mein tumne har box ko touch kar liya hoga.

Figure — Hardware-in-the-Loop (HIL) simulation — real hardware, simulated plant
Case class Kya cheez mushkil banati hai Covered by
A. Normal closed loop ordinary numbers, sab kuch range mein Ex 1
B. Real-time deadline PASS compute time comfortably step se kam Ex 2
C. Real-time deadline FAIL simulator bahut slow → loop toot jaata hai Ex 3
D. Zero / degenerate input duty cycle , ya start par Ex 4
E. Sign / direction flip negative torque, motor ulta ghoom raha hai Ex 5
F. Signal-conversion limits (clip, both rails) sensor voltage ya hit karti hai; current hit karta hai Ex 6
G. Real-world word problem full idle-speed scenario, settling time Ex 7
H. Exam-style twist "SIL yeh kyun miss karta hai par HIL kyun pakadta hai?" Ex 8
I. Limiting / steady-state , kaunsi speed par settle hoga? Ex 9

Hum numeric cases ke liye ek DC-motor plant reuse karte hain taaki numbers comparable rahein. Iske constants (sab invented but consistent):

Yeh parent note ki quasi-static update chain mein plug ho jaate hain (inductance term dropped, jaise upar define kiya):


Example 1 — Normal closed loop [Case A]

Forecast: pehle guess karo — speed upar jayegi, neeche, ya same rahegi? (Hint: kya motor ko back-EMF se zyada push kiya ja raha hai?)

  1. PWM se voltage. . Yeh step kyun? PWM duty cycle woh ek hi cheez hai jo ECU physically simulator ko deta hai; baaki sab isi se flow karta hai.

  2. Current. . Yeh step kyun? Voltage minus back-EMF resistance ke across net push hai; Ohm's law ise current mein convert karta hai. (, toh yahan koi clamp nahi chahiye.)

  3. Torque. . Yeh step kyun? Current torque banata hai — yeh woh Lorentz-force link hai jo actually shaft ko spin karta hai.

  4. Nayi speed (Euler). . Yeh step kyun? Newton's law kehta hai net torque over inertia angular acceleration hai; Euler us time step se multiply karta hai ek tick advance karne ke liye.

Verify: net torque positive hai, toh speed badhti hai — forecast se match karta hai ki back-EMF ko overpower karta hai. Units: ✓ (kyunki ). Nayi speed .


Example 2 — Deadline PASS [Case B]

Forecast: dono times add karo, step se compare karo. Pass ya fail?

Figure — Hardware-in-the-Loop (HIL) simulation — real hardware, simulated plant
  1. Total compute. . Yeh step kyun? Deadline sab kuch cover karta hai ECU command receive karne aur sensor answer deliver karne ke beech — compute aur I/O dono.

  2. Available budget. . Yeh step kyun? ECU har mein dobara poochta hai; jawab us se pehle ready hona chahiye.

  3. Compare aur utilisation lo. . Slack . Yeh step kyun? Parent note ka real-time law hai ; utilisation bas ise re-express karta hai ki "humne tick ka kitna fraction jaala?" — se kaafi kam hai.

Verify: utilisation matlab headroom, toh koi time dilation nahi — ECU kabhi notice nahi karta ki woh simulation mein hai. PASS.


Example 3 — Deadline FAIL [Case C]

Forecast: total vs. budget phir se — lekin is baar socho ECU kya experience karta hai.

  1. Total. . Yeh step kyun? Same accounting; galti sum mein dikhegi.

  2. Compare. . Overrun , utilisation . Yeh step kyun? utilisation cross karna ek missed hard deadline ki definition hai.

  3. Consequence. Simulator last-tick sensor values late deliver karta hai. ECU stale encoder counts padhta hai, old data par control compute karta hai, aur closed loop unstable ho sakta hai (woh "time dilation" jo parent note mein warn kiya gaya tha). Yeh step kyun? HIL tabhi honest rehta hai jab simulation keep up kare; ek baar lag hone par results meaningless hain.

Verify: overrun confirm karta hai; ki deficit ka matlab hai solver ko speed up karo (fixed-step, lookup tables, FPGA) ya loop slow karo. Fixes ke liye dekho FPGA for Real-Time Simulation aur Real-time Operating Systems (RTOS)FAIL.


Example 4 — Zero / degenerate input [Case D]

Forecast: zero volts aur zero speed ke saath, kya kuch move karta hai?

  1. Voltage. . Yeh step kyun? Duty cycle zero matlab PWM fully off hai — bilkul koi drive nahi.

  2. Current. . Yeh step kyun? Hum se divide karte hain, kisi aisi cheez se nahi jo zero ho sakti — toh formula rest par bhi safe rehta hai. Yeh degenerate check hai.

  3. Torque & speed. ; . Yeh step kyun? Koi current nahi → koi torque nahi → koi change nahi; motor correctly still rehta hai.

Verify: sab zeros, koi division by zero nahi (sirf denominator hai, ek fixed constant), speed unchanged at . Ek HIL rig jo yahan garbage produce karta woh Example 7 ke step 1 mein boot-sequence test fail karta. Clean.


Example 5 — Sign / direction flip [Case E]

Forecast: drive voltage ko back-EMF se compare karo. Kaunsa bada hai?

  1. Voltage. . Yeh step kyun? Tug-of-war ki drive side set karta hai.

  2. Back-EMF. . Yeh step kyun? Ek spinning motor apna khud ka voltage generate karta hai jo supply ka virodh karta hai; yahan yeh supply se bada hai.

  3. Current (negative ho jaata hai). . Yeh step kyun? Sign flip ho jaata hai — current ab ulta flow karta hai, matlab motor ek generator ki tarah act karta hai (braking). Ek HIL model ko yeh sign handle karna hi chahiye, warna braking scenarios galat test honge. (, koi clamp nahi.)

  4. Nayi speed. ; . Yeh step kyun? Negative torque plus damping decelerate karta hai — motor slow hota hai, jaise physics demand karta hai.

Verify: speed se par drop hui; current sign negative hai → regenerative braking sahi se capture hua. Sanity: back-EMF () drive () ⇒ braking ✓.


Example 6 — Signal & current limits: dono rails aur current ceiling [Case F]

Forecast: linear encoding se neeche aur se upar jaane ke liye khush hai — lekin hardware nahi. Teen temperatures mein se kaun clip hoga guess karo, aur kya stall current se aage nikal jaata hai.

Part (a): dono rails.

  1. Hot — upper rail. . ECU decode karta hai . Yeh step kyun? DAC apni top rail par saturate ho jaati hai; se upar har temperature same read karta hai — ek high-side blind spot.

  2. Cold — lower rail. . ECU decode karta hai . Yeh step kyun? Ek DAC pin par negative volts output nahi kar sakta, toh yeh par floor ho jaata hai — ECU sochta hai ki hai jabki plant actually par hai. Yeh lower-rail case upper rail jitna hi real hai aur ECU ke liye equally invisible.

  3. In range — koi clip nahi. , ke andar, toh aur exactly decode ho jaata hai. Yeh step kyun? Dikhata hai ki encoding sirf rail window ke andar faithful hai; fix yeh hai ki rescale karo taaki poora to span mein map ho.

Part (b): current ceiling.

  1. Raw stall current. , . Yeh step kyun? Standstill par koi back-EMF nahi hota, toh full supply current drive karta hai — yeh worst case hai jo winding ko stress karta hai.

  2. Ceiling tak clamp. , toh ek faithful model output karta hai , deta hai . Yeh step kyun? Real drivers current-limit karte hain; agar HIL model jaane deta toh over-predict karta torque aur miss karta ECU ki over-current protection logic (Fault Injection Testing target).

Verify (a): hot read karta hai (rail ) ✓; cold read karta hai (rail ) ✓; in-range exactly decode hota hai ✓ — dono rails aur clean middle sab dikhaye. Verify (b): clamp hota hai tak, ; bina clamp ke torque hota , ek over-estimate.


Example 7 — Real-world word problem: idle-speed test [Case G]

Forecast: sequence par nazar daalo — kya se doori kum ho rahi hai, ya badh rahi hai?

Figure — Hardware-in-the-Loop (HIL) simulation — real hardware, simulated plant
  1. PASS band. . Yeh step kyun? Test ka acceptance criterion ek fixed window hai; last value ko iske andar land karna chahiye.

  2. Last value check karo. ✓ → final reading par PASS. Yeh step kyun? Yahi literally parent ke Example 1 ka PASS criterion hai.

  3. Damping = setpoint ke baare mein error kam hoti hai. Settling ka sahi measure error hai , yaani har sample target se kitna door hai, step-to-step jump nahi. Compute karo: , , , . Pehle cranking transient ke baad errors fall karte hain — ek shrinking magnitude jo ko dono sides se straddle karta hai. Woh decaying, alternating-sign error ek damped (stable, settling) oscillation ka textbook signature hai. Yeh step kyun? Parent ne warn kiya tha ki growing swing matlab bahut high hai. Sahi test yeh hai ki error envelope decay kare; yahan karta hai, toh PID gains healthy hain.

  4. Unit conversion. . Yeh step kyun? Hamare plant equations use karte hain; convert karne se idle target seedha motor model ko feed ho sakta hai.

Verify: last value , ke andar ✓; setpoint errors transient ke baad decrease ho rahe hain ✓ (damped); (check: ✓). Is response ke peeche tuning ke liye dekho PID Control.


Example 8 — Exam-style twist [Case H]

Forecast: bug real silicon par real timing ke baare mein hai, ek live loop ke andar. Har level se do yes/no sawaal poochho — kya yeh real hardware run karta hai? kya yeh real-time loop close karta hai? — aur answers unhe rank karne do.

  1. MIL — miss karega. Controller abhi bhi sirf ek block-diagram model hai jo PC par run karta hai; koi code nahi, koi processor nahi, koi ISR nahi. lateness ke liye koi jagah nahi hai. Yeh step kyun? Tum ek hardware-timing bug ko kisi aisi cheez par reproduce nahi kar sakte jisme zero hardware ho.

  2. SIL — miss karega. Ab actual C code compile aur run hota hai, lekin PC par, target chip par nahi. PC timing ka microcontroller ki ISR latency se koi relation nahi, toh phir bug kabhi fire nahi hota. Yeh step kyun? SIL logic check karta hai, real interrupt timing nahi — bilkul wahi cheez jis par yeh bug depend karta hai.

  3. PIL — partially. Code real processor par run karta hai, toh ISR aur uska lateness ab genuinely occur karta hai aur variable corrupt kar sakta hai. Lekin plant abhi bhi PC se feed kiye gaye numbers hain, live real-time closed loop nahi, toh tum corruption dekh sakte ho uske full physical consequence ke bina. Yeh step kyun? PIL real silicon add karta hai (cause pakadta hai) lekin real-time signals nahi (effect nahi dikhata).

  4. HIL — poori tarah pakadta hai. Real ECU aur ek live closed loop: ISR genuinely microcontroller par late fire hoti hai, shared variable corrupt karta hai, ECU ek wrong actuator command emit karta hai, real-time plant simulator us wrong command par react karta hai aur altered sensor values wapas feed karta hai — toh fault visibly wrong closed-loop behaviour ke roop mein dikhti hai (jaise log par speed glitch). Yeh step kyun? HIL pehla level hai jisme dono real hardware timing aur live physical loop hain — exactly woh do ingredients jo is bug ko ek observable failure banane ke liye chahiye.

Verify: detection strength rank karta hai HIL PIL SIL MIL ek hardware-timing bug ke liye. Do boolean tests decide karte hain — "real chip?" (false, false, true, true) aur "live real-time loop?" (false, false, false, true) — aur HIL hi ek level hai jo dono par true score karta hai. Yeh parent note ke promise se match karta hai ki HIL "works in simulation but fails in hardware surprises" eliminate karta hai. Closure: jitna right test ko real hardware plus real signals ki taraf push karo, utne zyada timing-and-integration faults expose honge — yehi precisely woh reason hai ki HIL exist karta hai. (Iske around ek real vehicle add karo aur tum Vehicle-in-the-Loop (VIL) tak pahunch jaate ho.)


Example 9 — Limiting / steady state [Case I]

Forecast: steady state par, acceleration zero hai — toh net torque kya hona chahiye?

  1. Acceleration ko zero set karo. Steady state matlab , toh update mein bracket vanish hona chahiye: . Yeh step kyun? Limit ka poora point yahi hai: Euler increment vanish ho jaata hai, ek algebra equation bacha rehta hai, aur stepping band ho jaati hai.

  2. ke terms mein torque expand karo. aur ke saath: Yeh step kyun? Hum single unknown mein ek equation chahte hain.

  3. solve karo. Yeh step kyun? Rearrange karne se steady speed isolate hoti hai; shared constants plug karne se woh number milta hai jis par HIL log asymptote hona chahiye.

Verify: par: back-EMF , current ( se kaafi kam), torque , damping torque — equal, toh net torque ✓. Steady state , aur note karo ki yeh Example 1 ke one-step se upar baithta hai, confirm karta hai ki motor abhi bhi wahan accelerate kar raha hai.


Recall Quick self-test

par one-step new speed (Ex 1)? ::: Utilisation jab compute, step (Ex 2)? ::: , PASS Overrun jab compute, step (Ex 3)? ::: , FAIL Current sign jab back-EMF (V) drive (V) ko beat kare (Ex 5)? ::: negative, (braking) Cold ko V pin par encode karne se kya read hoga (Ex 6)? ::: (lower rail par floored) par stall current clamp se pehle/baad (Ex 6)? ::: raw → clamped to Steady-state speed at (Ex 9)? :::


Connections: yahan ki plant math parent HIL note se aati hai; timing budget Real-time Operating Systems (RTOS) aur FPGA for Real-Time Simulation se link karta hai; idle-speed loop PID Control aur PWM (Pulse Width Modulation) use karta hai; temperature/current failure cases Fault Injection Testing se connect karte hain aur sensor frames CAN Bus Protocol se; test-level ranking Model-in-the-Loop (MIL), Software-in-the-Loop (SIL), Processor-in-the-Loop (PIL) aur Vehicle-in-the-Loop (VIL) ko touch karti hai.