Visual walkthrough — DMA — memory-to-memory, peripheral-to-memory without CPU

5.5.8 · D2 · Coding › Embedded Systems & Real-Time Software › DMA — memory-to-memory, peripheral-to-memory without CPU

Hum sirf yeh assume karenge: data numbered locations ("addresses") pe rehta hai, aur ek shared road (bus) ek waqt mein sirf ek item carry karti hai. Agar yeh dono ideas naye hain, toh Memory-Mapped IO aur Bus Arbitration pe ek nazar daalo — lekin tum inke bina bhi follow kar sakte ho.

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Step 1 — Ek item, ek trip: "beat"

YAHAN se kyun shuru karein? Kyunki ek bada transfer kuch nahi hai sirf bahut saare identical beats ka. Agar hum ek beat ki cost exactly samajh lein, toh million ki cost sirf multiply karne se milti hai. Yahi poora trick hai — atom dhundo, phir atoms gino.

PICTURE. Neeche, violet box orange road pe address $S$ (source) se address $D$ (destination) tak jaata hai. Yeh single journey ek beat hai.

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Step 2 — Ek beat ki cost kya hai: cycles aur clock

Do symbols carefully earn karte hain:

• $f$ — bus clock frequency. Yeh hai har second mein kitne ticks hote hain. Iska unit hertz (Hz) = ticks per second hai. Ek $48\text{MHz}$ bus har second mein $48,000,000$ baar tick karti hai.
• $c$ — cycles per beat. Yeh hai ek box-carry mein kitne ticks lagte hain. Fast on-chip RAM ke liye, $c=1$: ek tick, ek box. Ek slow peripheral bol sakta hai "ruko, main ready nahi hoon" aur beat ko $c=2,3,\dots$ ticks tak stretch kar deta hai — yeh extra ticks wait states kehlate hain.

Yeh dono kyun, aur koi, jaise metres per second mein speed kyun nahi? Kyunki hardware ko distance ka koi concept nahi — use sirf ticks pata hain. Chip pe time hamesha "kitne ticks × har tick kitni der ka" hota hai. Toh ek beat ki natural cost hai:

$t_{\text{beat}}=\underset{\begin{array}{c}\text{ticks used}\\ \text{by one beat}\end{array}}{\underbrace{c}}\times \underset{\begin{array}{c}\text{seconds}\\ \text{per tick}\end{array}}{\underbrace{\frac{1}{f}}}=\frac{c}{f}$

Equation ko term by term padhein: $\frac{1}{f}$ matlab "ek tick kitni der ka hai?" — agar ek second mein $f$ ticks hain, toh har tick $1/f$ seconds ka hai. $c$ ticks se multiply karo aur tumhare paas ek beat ke seconds aa jaate hain. $f$ neeche aur frequency ka "per second" ek hi baat hai, do tarike se likhi hui.

PICTURE. Metronome tick karta hai; ek beat exactly $c$ chote tick-boxes fill karta hai.

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Step 3 — Beats gino: transfer-time formula

Multiply kyun karein, koi smart addition kyun nahi? Kyunki beats identical aur sequential hain — ek road, ek baar mein ek box (CPU road share kare, yeh Step 7 mein dekhenge). $N$ equal costs ek row mein hain toh exactly multiplication hai. Koi hidden overhead nahi ignore ho rahi sirf ek tiny one-time setup ke alaawa, jo $N$ ke saath grow nahi karta.

$t_{\text{DMA}}=\underset{\begin{array}{c}\text{how many}\\ \text{beats}\end{array}}{\underbrace{N}}\times \underset{\begin{array}{c}\text{cost of}\\ \text{one beat}\end{array}}{\underbrace{t_{\text{beat}}}}=N\cdot \frac{c}{f}=\boxed{\frac{Nc}{f}}$

Padhte hain: zyada items ($N\uparrow$) → zyada time. Slow beats ($c\uparrow$, wait states) → zyada time. Faster clock ($f\uparrow$, neeche) → kam time. Har arrow wahi direction point karta hai jo tumhara gut expect karta hai — yeh sign hai ki formula honest hai.

PICTURE. $N$ boxes ki ek row; total time woh $N$ tick-groups ki row hai jo end-to-end lagti hai.

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Step 4 — Har item ki ek width hoti hai: sirf boxes nahi, bytes

Width matter kyun karta hai agar ek beat phir bhi $c/f$ hi lagta hai? Yahan beautiful part hai: ek wide beat ek narrow wale jitna hi same $c/f$ seconds leta hai — road same width ka hai, ek shove poora item carry karta hai. Toh $w$ bada karne se same time mein zyada bytes milte hain. Yeh free speed hai, agar tumhara data aligned ho toh.

Total bytes moved: $B=\underset{\text{items}}{\underbrace{N}}\times \underset{\text{bytes each}}{\underbrace{w}}=Nw$

PICTURE. Same number of beats, lekin ab har box pe "$w$ bytes" stamp laga hai. $w=4$ wala box ek hi trip mein chaar chote byte-tiles carry karta hai.

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Step 5 — Throughput: $N$ kyun gayab ho jaata hai

Rate compute kyun karein? Kyunki "yeh channel kitna fast hai?" ko is baat pe depend nahi karna chahiye ki tum kitna bhej rahe ho. Ek firehose ki ek rate hoti hai chahe ek second chalaao ya das. Hum prove karne wale hain ki DMA channel bhi aise hi behave karta hai.

$$\text{Throughput}=\frac{B}{t_{\text{DMA}}}=\frac{Nw}{\frac{Nc}{f}}=\frac{Nw\cdot f}{Nc}=\frac{\cancel{N}wf}{\cancel{N}c}=\boxed{\frac{wf}{c}}$$

Cancellation padhte hain: upar bytes hain ($\propto N$), neeche time hai ($\propto N$). Dono $N$ ke saath same rate se badhte hain, isliye unka ratio $N$ bhool jaata hai. Jo bachta hai — $wf/c$ — woh channel ki property hai: wider items, faster clock, kam wait-cycles → faster. 10 items bhejo ya 10 million; rate identical hai.

PICTURE. Bahut alag length ($N$ small vs $N$ large) ke do transfers pipes ki tarah draw kiye — same diameter — same rate, different pipe length.

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Step 6 — Address generation: boxes kahan se uthaye aur kahaan rakhe jaate hain

Steps kabhi kabhi zero kyun hote hain? Kyunki address pe kya hai, us wajah se. RAM buffer ek slots ki row hai — isko fill karne ke liye har baar $w$ se forward step karna padta hai. Lekin peripheral ka data register (jaise ADC->DR) ek fixed hardware address hai; naye samples same spot pe appear hote hain jab bhi peripheral ready hota hai. Isko step karna DMA ko unrelated registers mein le jaayega — silent corruption. Isliye:

Direction	${\Delta }_S$	${\Delta }_D$	Kyun
Mem→Mem	$w$	$w$	dono buffers hain, dono aage badhao
Periph→Mem	$0$	$w$	ek fixed register padho, slots mein scatter karo
Mem→Periph	$w$	$0$	slots se gather karo, ek fixed register ko feed karo

PICTURE. Left: mem→mem, dono pointers march karte hain. Right: periph→mem, source pin ek register pe pinned rehta hai jabki destination pointer buffer mein walk karta hai.

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Step 7 — Degenerate aur edge cases (kuch bhi hidden nahi)

Case $N=0$ (empty transfer). $t=0\cdot c/f=0$. Zero beats, zero time — controller simply "complete" immediately fire kar deta hai. Tumhara code phir bhi us flag ka wait kare (jaldi read mat karo!).

Case $N=1$ (single item). $t=c/f$: exactly ek beat. Yeh sabse chota real transfer hai; yahan one-time setup cost (jo humne ignore ki) actually dominate karti hai — ek word ke liye, plain CPU load/store often DMA program karne se sasta hota hai.

Case $c>1$ (wait states). Ek slow peripheral har beat stretch karta hai. $t=Nc/f$, $c$ mein linearly badhta hai; throughput $wf/c$ shrink karta hai. Ab peripheral, bus nahi, bottleneck hai — isliye ek slow ADC and DAC ko sirf faster clock se speed up nahi kiya ja sakta.

Case: road sharing (bus arbitration). Ab tak DMA ke paas bus thi. Reality: CPU bhi chahta hai, aur sirf ek drive kar sakta hai — ek arbiter decide karta hai (Bus Arbitration). Cycle-stealing mode mein DMA ek beat leta hai phir road wapas deta hai, toh CPU starve nahi hota lekin DMA thoda slow hota hai. Burst mode mein DMA puri block ke liye road hold karta hai — fastest DMA, lekin CPU kisi bhi memory access pe stall ho sakta hai. Hamara $t=Nc/f$ ideal, uninterrupted time hai; real time $\ge$ us se hai.

PICTURE. Do timelines. Top (burst): ek lamba violet block, CPU stalled. Bottom (cycle-steal): violet beats orange CPU cycles ke saath interleaved — dono progress karte hain.

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Ek-picture summary

Sab kuch ek canvas pe: ek beat $c/f$ seconds leta hai → $N$ beats $Nc/f$ lete hain → har beat $w$ bytes carry karta hai toh $B=Nw$ → bytes ko time se divide karo, $N$ cancel hota hai aur channel rate $wf/c$ milti hai. Address steps ($\Delta$) pattern decide karte hain; arbitration real (non-ideal) timing decide karta hai.

Recall Feynman: poora walkthrough retell karo

Socho ek robot boxes ek room mein carry kar raha hai, ek box per shove. Ek shove mein ek fixed number of clock ticks ($c$) lagte hain, aur clock $f$ baar second mein tick karti hai — toh ek box $c/f$ seconds leta hai. $N$ boxes line mein lagao aur yeh bas itna hi hai, $N$ baar: $Nc/f$. Ab har box chota ya bada ho sakta hai ($w$ bytes) — ek bada box same shove leta hai lekin zyada deliver karta hai, toh total stuff $Nw$ bytes hai. Poocho "stuff kitni tez aata hai?" aur stuff ko time se divide karo: upar aur neeche ke $N$ cancel ho jaate hain, kyunki boxes double karne se stuff aur time dono double hote hain. Jo bachta hai, $wf/c$, woh sirf robot-aur-room combo ki quality hai — box size, tick speed, ticks per shove. Robot kahan se uthata aur kahaan drop karta hai yeh do step-sizes se set hota hai; agar woh ek peripheral ke single mailbox se grab kar raha hai, toh woh step zero hai toh woh same slot mein haath dalte rehta hai. Aur room mein ek darwaza hai: kabhi kabhi brain (CPU) ko bhi chahiye, toh yeh turn lete hain — isliye real transfers kabhi bhi utni fast nahi hoti jitni clean $Nc/f$ bolti hai.

Recall

Ek beat ka time ::: $c/f$ (cycles per beat ÷ ticks per second). Throughput se $N$ kyun gayab hota hai? ::: Bytes ($Nw$) aur time ($Nc/f$) dono $N$ ke saath scale karte hain, toh unka ratio isko drop kar deta hai. Periph→mem ke liye ${\Delta }_S=0$ kyun? ::: Peripheral data register ek fixed address hai; naye items same spot pe appear hote hain. Real transfer time vs $Nc/f$? ::: $\ge Nc/f$, kyunki CPU bus share karta hai (arbitration), cycle-steal mode mein DMA stall ho sakta hai.