5.5.8 · D5 · HinglishEmbedded Systems & Real-Time Software
Question bank — DMA — memory-to-memory, peripheral-to-memory without CPU
5.5.8 · D5· Coding › Embedded Systems & Real-Time Software › DMA — memory-to-memory, peripheral-to-memory without CPU
Shuru karne se pehle, kuch symbols aur words apni jagah earn karte hain taaki kuch bhi surprise na kare:
True or false — justify
TRUE / FALSE: DMA transfers koi bhi clock cycles use kiye bina hote hain.
False. DMA CPU ke compute pipeline ko free karta hai, lekin har beat phir bhi bus cycles aur bus bandwidth consume karta hai — yeh CPU ke liye free hai, memory subsystem ke liye nahi.
TRUE / FALSE: Kyunki CPU copy loop execute nahi kar raha, DMA transfer ke dauran woh kabhi stall nahi ho sakta.
False. CPU aur DMA ek bus share karte hain; burst mode mein DMA bus ko itni der tak hold kar sakta hai ki CPU memory access ko wait karna padta hai. Cache se compute theek hai, lekin cache miss stall kar sakta hai.
TRUE / FALSE: Item width double karne se same number of bytes ke liye transfer time roughly half ho jaata hai.
True. Same bytes ke liye wider items matlab fewer beats. Kyunki aur double hone par half hota hai, time half ho jaata hai — exactly isliye aap widest aligned width choose karte ho.
TRUE / FALSE: Throughput batata hai ki zyada data transfer karne se zyada bytes/second milte hain.
False. mein cancel ho jaata hai; throughput ek rate hai, width, clock, aur cycles-per-beat se fix hoti hai. Zyada data proportionally zyada time leta hai, isliye rate unchanged rehti hai.
TRUE / FALSE: Peripheral-to-memory transfer ke liye aapko har beat mein source aur destination dono address increment karne chahiye.
False. Peripheral ka data register ek fixed hardware address hai, isliye ; sirf RAM buffer aage chalta hai (). Source increment karna neighbouring registers mein wander kar deta hai.
TRUE / FALSE: "Start DMA" function call karne ke baad, destination buffer bilkul agle line pe valid data hold karta hai.
False. DMA asynchronous hai; aapko transfer-complete flag ya interrupt ka wait karna padta hai. Pehle read karne par partial ya stale bytes milte hain.
TRUE / FALSE: Data cache waale microcontroller pe, DMA input seedha RAM mein likhne se guarantee hoti hai ki CPU fresh bytes padhega.
False. CPU ek cached stale copy return kar sakta hai. DMA-filled RAM padhne se pehle aapko cache region invalidate karna padta hai — dekho Cache Coherency.
TRUE / FALSE: Cycle-stealing arbitration hamesha burst arbitration se fast hoti hai.
False. Cycle-stealing har beat ke baad bus release karta hai, CPU latency protect karta hai lekin re-arbitration overhead add karta hai. Burst bus hold karta hai aur jaldi finish karta hai — yeh latency-vs-throughput trade hai, koi clear winner nahi.
TRUE / FALSE: Mem-to-mem DMA aur haath se likha memcpy destination mein identical bytes produce karte hain.
True (byte contents ke liye), lekin cost profile alag hai: DMA kaam offload karta hai jabki memcpy poore waqt CPU ko busy rakhta hai.
TRUE / FALSE: Hardware-triggered peripheral transfer enable karte hi poora block move ho jaata hai.
False. Yeh ek DMA request per ek beat perform karta hai; peripheral tab request raise karta hai jab uske paas item ho ya use zaroorat ho, isliye transfer naturally peripheral ki data rate se pace hota hai.
Spot the error
ERROR? "Maine UART receive DMA set up kiya, isliye incoming bytes mein walk karne ke liye har beat mein source address 1 se increment kiya."
Error. UART data register ek single fixed address hai; nayi bytes wahan baar baar aati hain. rakho aur sirf RAM destination increment karo.
ERROR? "4096 bytes fastest copy karne ke liye maine use kiya taaki zyada beats hon aur jaldi khatam ho."
Error. Zyada beats matlab slower. Widest aligned width use karo (): 4096 ki jagah 1024 beats, roughly 4× faster.
ERROR? "Mera ADC-capture buffer corrupt lag raha tha, isliye maine transfer enable karne se pehle while(!done_flag); add kiya."
Error. Transfer run hone se pehle flag kabhi set nahi ho sakta — yeh forever spin karega. Wait transfer enable karne ke baad aata hai, buffer padhne se pehle.
ERROR? "DMA ko interrupt ki zaroorat nahi thi, isliye maine transfer-complete IRQ disable kar diya aur thodi der baad buffer use kar liya."
Error. Fixed delay ek race hai: bus contention ya wait-states transfer ko aapke guess se zyada stretch kar sakte hain. Truly done hone ki guarantee ke liye flag/interrupt use karo.
ERROR? "DMA ka input RAM mein likhna finish hone ke baad maine cache flush kiya taaki data valid ho jaaye."
Error. DMA input ke liye aap padhne se pehle invalidate (stale cached copies drop) karte ho; DMA output ke liye (CPU ne likha, DMA padh raha hai) DMA shuru hone se pehle clean/flush karte ho. Direction aur timing dono galat tha.
ERROR? "Throughput 96 MB/s hai, isliye 96 MB transfer item width chahe jo bhi ho 1 second leta hai."
Error. Throughput khud width pe depend karta hai (). change karo aur 96 MB/s figure change ho jaata hai; yeh setup se independent koi fixed budget nahi hai.
ERROR? "Maine source, count aur mode program kiya, enable hit kiya, aur expect kiya ki mem-to-mem run ho — lekin kuch move nahi hua."
Error. Aap destination address bhool gaye (aur mem-to-mem ke liye, ek software trigger). Setup checklist S.C.A.M. yaad karo — Source, Count, Address-increment mode, Mode/trigger — woh chaar fields jo enable karne se pehle har DMA ko chahiye; yahan destination (address setup ka part) missing tha.
Why questions
WHY peripheral ka source address fixed rehta hai jabki destination aage chalta hai?
Peripheral ek hardware register (memory-mapped) expose karta hai jahan har nayi item same spot pe aati hai; RAM buffer ko woh items successive slots mein scatter karna hota hai, isliye sirf wahi increment hota hai.
WHY throughput formula se cancel ho jaata hai lekin transfer-time formula se nahi?
Time move ki gayi amount ke saath scale karta hai, lekin throughput = bytes/time = — bytes aur time dono mein cancel ho jaate hain, sirf yeh rate bachti hai ki har beat kitni fast hai.
WHY hardware-triggered transfer peripheral ke saath "naturally rate-matched" hota hai?
Peripheral exactly ek DMA request raise karta hai har item ke liye jo uske paas hai/chahiye, aur DMA har request pe ek beat run karta hai — isliye yeh kabhi peripheral ki pace se aage ya peeche nahi hota.
WHY DMA fast peripheral data capture kar sakta hai jo CPU miss kar sakta hai?
Ek dedicated engine hardware mein deterministic, tiny latency ke saath har request pe respond karta hai, jabki CPU mid-instruction ho sakta hai ya kisi aur ISR ko service kar raha ho aur microsecond-fast ADC sample ke liye late aa sakta hai.
WHY cache coherency sirf kuch chips pe problem hai, simplest MCUs pe nahi?
Simple MCUs mein data cache nahi hoti, isliye CPU aur DMA dono same RAM directly dekhte hain. Cache add karo aur CPU ek private stale copy hold kar sakta hai, toh RAM aur cache mein disagreement ho sakti hai — yahi coherency bug hai.
WHY burst se pehle cycle-stealing choose karein jabki burst block jaldi finish karta hai?
Cycle-stealing har beat ke baad bus release karta hai taaki CPU kabhi zyada wait na kare — aap ek slower overall transfer ke badle guaranteed low CPU latency lete ho, jo real-time deadlines demand karta hai.
WHY DMA double/circular buffering ke saath itna achha kaam karta hai?
DMA ek buffer fill karta hai jabki CPU doosra process karta hai; circular buffer ke saath address auto-wrap karta hai, jisse ek continuous stream hamesha ke liye bina CPU ke har block mein intervene kiye chal sakti hai.
Edge cases
EDGE: Agar aapne item count set kiya toh?
Koi beats schedule nahi hote, kuch transfer nahi hota aur (kai controllers pe) complete flag turant fire ho sakta hai — "done bolta hai lekin buffer empty hai" confusion ka ek common source.
EDGE: Agar mem-to-mem copy mein source aur destination memory regions overlap karen toh?
DMA mein generally safe
memmove jaisi koi overlap protection nahi hoti; forward-incrementing addresses un bytes ko overwrite kar sakte hain jo abhi copy nahi hue, result corrupt ho jaata hai. Overlap avoid karo ya safe direction mein copy karo.EDGE: Agar item width 4 hai lekin buffer address 4-byte aligned nahi hai toh?
Kai buses fault karte hain ya silently access split karte hain; aap width advantage kho dete ho ya bus error aata hai. Widest-width tabhi help karta hai jab addresses us width ke liye aligned hon.
EDGE: Agar peripheral DMA ke requests service karne se faster data produce kare toh?
Overrun hota hai — nayi data register mein aa jaati hai pehle hi wala beat consume kare, aur bytes lost ho jaate hain. Peripheral usually ek overrun error flag raise karta hai.
EDGE: Agar CPU aur DMA dono ek hi cycle mein bus chahte hon toh?
Arbiter exactly ek ko grant karta hai; doosra ek arbitration slot wait karta hai. Sirf ek driver kabhi bhi shared bus hold karta hai, isliye koi corrupt nahi karta — ek briefly stall ho jaata hai bas.
EDGE: Agar enable bit beech mein clear kar diya jaaye toh transfer ka kya hoga?
Transfer current beat pe abort ho jaata hai, destination partially filled rehta hai — completed beats valid hain, baaki untouched hain, aur koi complete-interrupt fire nahi hota.
EDGE: Aapka controller negative (decrementing) address increment () support karta hai. Yeh sahi choice kab hai?
Jab aapko buffer backwards traverse karna ho — jaise ek byte array in place reverse karna, ya ek overlap jahan high-to-low copy karna unread bytes clobber karne se bachata hai. Controller tab walk karta hai ki jagah; time aur throughput identical hain (same , , , ) — sirf address walking ki direction change hoti hai.
Recall Ek-line takeaways
DMA compute ke liye free hai, bus ke liye nahi ::: yeh hamesha bus cycles cost karta hai aur CPU ko memory access pe stall kar sakta hai. Peripheral address fixed hai ::: sirf RAM side increment karo. Hamesha done flag ka wait karo ::: DMA asynchronous hai. Cache + DMA ko manual invalidate/clean chahiye ::: RAM aur cache disagree kar sakte hain. Address increment positive, zero, ya negative ho sakta hai ::: forward walk, fixed register, ya backward walk.