5.5.6 · D5Embedded Systems & Real-Time Software
Question bank — CAN bus — frame format, arbitration, error handling — critical in aerospace
Before you start, keep three anchors in mind:
- Dominant = 0, recessive = 1. The bus is the AND of everything sent.
- Lower ID wins arbitration — because a leading 0 (dominant) beats a leading 1 (recessive).
- Error counters climb fast for the offender (+8) and heal slow (−1), so a broken node benches itself.
True or false — justify
Every node on a CAN bus needs a unique hardware address to receive messages.
False. CAN is message-oriented, not node-oriented — frames carry an ID describing the content, and every node filters by ID; no node ever has a personal address.
If two nodes send the exact same ID at the same time, the bus is corrupted.
False for arbitration itself — identical bits AND to the same value, so nothing breaks there; but two nodes sending the same ID with different data will collide later and trigger a bit/CRC error, so unique IDs per source are still required by design.
A recessive bit only appears on the bus if every single node sends recessive.
True. Recessive = 1, and the wired-AND outputs 1 only when all inputs are 1 — one dominant sender anywhere forces the bus to 0.
An extended (29-bit) frame always outranks a standard (11-bit) frame.
False. When their 11-bit bases match, the standard frame wins because its dominant RTR/IDE bit beats the extended frame's recessive SRR at that arbitration position — the extra extended control bits are designed not to steal priority.
CAN arbitration works like Ethernet: on a collision both frames are destroyed and both retry.
False. That describes CSMA-CD. CAN is non-destructive — the highest-priority frame proceeds untouched while losers merely defer and retransmit later, losing zero data.
The ACK slot means each individual receiver sends a personal acknowledgment.
False. The ACK is collective: the transmitter sends the slot recessive, and any receiver that passed CRC pulls it dominant. The transmitter learns "at least one node heard me," not which nodes.
Bit stuffing is done to slow the transmitter down.
False. Bit stuffing inserts an opposite bit after 5 identical ones so receivers get regular edges for clock recovery; it's about resynchronization, not throttling.
An Overload Frame and an Error Frame do the same job.
False. Both are 6 dominant bits, but an Error Frame aborts a corrupt data frame and forces retransmission, while an Overload Frame is raised during intermission to buy a short delay and never discards data.
A Bus-Off node is permanently dead and must be power-cycled.
False. Bus-Off is recoverable: after observing 128 sequences of 11 consecutive recessive bits (bus idle), the node may rejoin with counters reset — recovery is part of the spec.
The CRC field guarantees the message content is correct in meaning.
False. CRC detects transmission bit errors — it says "the bits I received match the bits sent." A logically wrong value sent by a healthy node passes CRC perfectly.
Assigning your fire-alarm message the highest ID number gives it top priority.
False and dangerous. Lowest numeric ID wins; give a fire alarm
0x001, never 0x7FF, because more leading dominant (0) bits keeps it on the bus.Spot the error
"During arbitration, a node that reads dominant while sending dominant has lost and backs off."
Wrong. You only lose when you send recessive (1) but read dominant (0) — that means someone higher-priority is driving the bus. Sending 0 and reading 0 is agreement; you stay in.
"A stuff error is declared after 5 identical consecutive bits."
Wrong. A stuff bit is inserted after 5 identical bits; the stuff error fires when 6 identical bits are seen, meaning the stuffing rule was violated (or an error flag was raised deliberately).
"A form error and a CRC error are the same check."
Wrong. A form error is a fixed-format field (delimiter, EOF) holding an illegal value; a CRC error is a checksum mismatch. They are two of the five independent guardians (bit, stuff, CRC, form, ACK), each catching a different failure mode.
"On any error the transmitter adds 1 to TEC and heals by subtracting 8."
Backwards. On error the transmitter adds +8 to its Transmit Error Counter (TEC); on success it subtracts −1. The asymmetry punishes the offender 8× faster than it heals, driving a faulty transmitter toward Error-Passive and Bus-Off.
"An Error Frame is carefully bit-stuffed so it looks like a normal frame."
Wrong. An active Error Frame is 6 dominant bits that deliberately violate bit stuffing, so every node is forced to notice the error and discard the frame globally.
"The DLC field lets a bigger payload win arbitration."
Wrong. Priority is decided only during the ID field. The Data Length Code (DLC) and Data are transmitted after arbitration is already settled and never affect who wins.
"IDE and RTR are payload bits, so they don't matter until after arbitration."
Half-wrong. RTR (Remote Transmission Request) and IDE (Identifier Extension) sit inside/adjacent to the arbitration window, so they can decide priority — e.g. a data frame (RTR=0, dominant) beats a remote frame (RTR=1) of the same ID.
Why questions
Why is dominant defined as logic 0 rather than logic 1?
Because in an AND a single 0 forces the result to 0, so the node sending 0 "wins" the open-collector bus for free — arbitration falls out of the electrical rule with no referee.
Why can arbitration be lossless when Ethernet collisions are not?
On CAN the bus value is a live AND that each node reads back bit by bit, so a loser detects the conflict mid-ID and steps aside before its data is even sent; Ethernet detects collisions only after both frames have already scrambled on the wire.
Why does an extended (29-bit) ID need its own extra control bits (SRR and IDE) inside the arbitration field?
So the two frame types can share one wired-AND contest cleanly: SRR (recessive) sits where the standard RTR sat and IDE marks "29-bit follows," and their recessive values guarantee an extended frame never accidentally out-prioritizes a standard frame with the same base ID.
Why does the transmitter increment TEC by 8 but decrement by only 1?
To achieve fault confinement — a node causing errors climbs toward Bus-Off far faster than it can heal, so one bad LRU silences itself rather than jamming a safety-critical bus, which is exactly what DO-178C/254 systems require.
Why does the ACK slot use a collective dominant overwrite instead of named replies?
A single dominant pull proves "≥1 healthy receiver exists" in one bit-time with no addressing overhead, matching CAN's message-broadcast model where the sender doesn't need to know who is listening.
Why must all nodes discard a frame when one node raises an error flag?
Consistency — if some nodes accepted a frame and others rejected it, data would diverge across the network; the globally-visible Error Frame forces a uniform "everyone drop and retransmit" decision.
Why is CAN's fixed EOF/delimiter format checked as a "form error"?
Those fields must hold specific recessive/dominant values, so any deviation reveals corruption at a point where CRC alone might not localize it — a cheap independent guardian on top of CRC.
Why does an Overload Frame exist at all if a node can just wait for the bus to go idle?
A slow receiver may need a moment right after a frame, during intermission, before the next one starts; the Overload Frame lets it force that delay actively rather than risk missing a back-to-back frame it isn't ready for.
Why does lower ID naturally correspond to more urgent messages in aerospace?
Because engineers assign it that way, exploiting that fewer leading 1s = smaller number = wins the wired-AND; conventions like ARINC 825 standardize this so a fire alarm outranks a cabin-light status by construction.
Edge cases
What happens if two nodes transmit identical full frames (same ID and data)?
They agree bit-for-bit through arbitration and payload, so neither loses — both effectively transmit the same frame and both consider it sent; this is why source uniqueness is a design rule, not an accident.
What is the bus state when no node is transmitting?
Idle = recessive (1), because with nothing pulling dominant the open-collector line floats high; a falling edge (SOF, dominant 0) is what wakes listeners.
When exactly may a node start a new frame after the previous one ends?
Only after EOF plus Intermission (3 recessive bits of Inter-Frame Space) have passed and the bus is idle — starting during intermission is forbidden (that window is reserved for Overload Frames).
Can a node win arbitration and then still fail to deliver its frame?
Yes. It wins the ID contest but can later hit a bit, CRC, form, or ACK error (nobody heard it) — winning arbitration only grants the floor, not guaranteed delivery.
What happens during arbitration if a node sends its ID but the bus is already mid-frame?
It doesn't start — a node waits for the bus to be idle (recessive) plus the inter-frame space before attempting SOF, so it never barges into another node's ongoing frame.
What happens if a node in Error-Passive state detects yet another error while transmitting?
Its TEC (Transmit Error Counter) keeps climbing; once TEC exceeds 255 it enters Bus-Off and stops driving the bus entirely, isolating the fault while other nodes continue normally.
If REC (Receive Error Counter) alone climbs, can a node reach Bus-Off?
No. Bus-Off is triggered by TEC > 255 only; a pure witness (high REC) can at most become Error-Passive, because it isn't the one causing the errors.
How does a bit error get ignored on purpose during arbitration and ACK?
In those windows a mismatch (sent recessive, read dominant) is the expected signal of losing arbitration or receiving an acknowledgment — so the bit-error check is suppressed there to avoid false alarms.
Recall One-line self-test before you close the page
Sent-recessive-read-dominant means what, and where is it not an error? ::: It means "someone higher priority is driving" — a normal loss of arbitration (or a valid ACK), not an error, precisely in the arbitration and ACK slots.
Connections
- Parent: 5.5.06 CAN bus — frame format, arbitration, error handling — critical in aerospace (Hinglish)
- Electrical foundation: Wired-AND logic, Open-collector buses
- Contrast: CSMA-CD (Ethernet)
- Integrity: CRC cyclic redundancy check, Bit stuffing and clock recovery
- Aerospace context: DO-178C / DO-254 aerospace certification, ARINC 825, Real-Time scheduling