5.5.6 · D5 · HinglishEmbedded Systems & Real-Time Software

Question bankCAN bus — frame format, arbitration, error handling — critical in aerospace

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5.5.6 · D5 · Coding › Embedded Systems & Real-Time Software › CAN bus — frame format, arbitration, error handling — critic

Shuru karne se pehle, teen anchors dhyan mein rakho:

  • Dominant = 0, recessive = 1. Bus har cheez jo bheja gaya uska AND hai.
  • Lower ID arbitration jeet ta hai — kyunki ek leading 0 (dominant) ek leading 1 (recessive) ko beat karta hai.
  • Error counters offender ke liye tezi se badhte hain (+8) aur dheere theek hote hain (−1), isliye ek broken node khud ko bench kar leta hai.
Figure — CAN bus — frame format, arbitration, error handling — critical in aerospace
Figure — CAN bus — frame format, arbitration, error handling — critical in aerospace
Figure — CAN bus — frame format, arbitration, error handling — critical in aerospace
Figure — CAN bus — frame format, arbitration, error handling — critical in aerospace
Figure — CAN bus — frame format, arbitration, error handling — critical in aerospace

True or false — justify

Ek CAN bus par har node ko messages receive karne ke liye ek unique hardware address chahiye.
False. CAN message-oriented hai, node-oriented nahi — frames ek ID carry karte hain jo content describe karta hai, aur har node ID ke basis par filter karta hai; kisi node ka kabhi koi personal address nahi hota.
Agar do nodes same time par exact same ID bhejte hain, toh bus corrupt ho jaati hai.
Arbitration ke liye False — identical bits AND ho ke same value dete hain, isliye wahan kuch nahi toot ta; lekin do nodes same ID alag data ke saath bhejein toh baad mein collide karenge aur bit/CRC error trigger karenge, isliye unique IDs per source design rule hai.
Ek recessive bit bus par tab hi appear hota hai jab har single node recessive bhejta hai.
True. Recessive = 1, aur wired-AND 1 output tab hi karta hai jab sabhi inputs 1 hon — kahin bhi ek dominant sender bus ko 0 force kar deta hai.
Ek extended (29-bit) frame hamesha ek standard (11-bit) frame se zyada rank rakhta hai.
False. Jab unke 11-bit bases match karte hain, standard frame jeet ta hai kyunki uska dominant RTR/IDE bit us arbitration position par extended frame ke recessive SRR ko beat karta hai — extra extended control bits specifically is liye design kiye gaye hain ki woh priority na chura sakein.
CAN arbitration Ethernet ki tarah kaam karta hai: collision par dono frames destroy ho jaate hain aur dono retry karte hain.
False. Yeh CSMA-CD describe karta hai. CAN non-destructive hai — highest-priority frame untouched proceed karta hai jabki losers sirf defer karte hain aur baad mein retransmit karte hain, zero data lose hota hai.
ACK slot ka matlab hai har individual receiver ek personal acknowledgment bhejta hai.
False. ACK collective hai: transmitter slot recessive bhejta hai, aur koi bhi receiver jo CRC pass kar chuka hai use dominant pull karta hai. Transmitter sirf yeh jaanta hai "kam se kam ek node ne mujhe suna," kaun sa node nahi.
Bit stuffing transmitter ko slow karne ke liye kiya jaata hai.
False. Bit stuffing 5 identical bits ke baad ek opposite bit insert karta hai taaki receivers ko clock recovery ke liye regular edges milein; yeh resynchronization ke baare mein hai, throttling ke baare mein nahi.
Ek Overload Frame aur ek Error Frame same kaam karte hain.
False. Dono 6 dominant bits hain, lekin ek Error Frame ek corrupt data frame ko abort karta hai aur retransmission force karta hai, jabki Overload Frame intermission ke dauran raise kiya jaata hai thodi der kharidne ke liye aur kabhi data discard nahi karta.
Ek Bus-Off node permanently dead hai aur use power-cycle karna padta hai.
False. Bus-Off recoverable hai: 128 sequences of 11 consecutive recessive bits (bus idle) observe karne ke baad, node counters reset ke saath rejoin kar sakta hai — recovery spec ka hissa hai.
CRC field guarantee karta hai ki message content meaning mein correct hai.
False. CRC transmission bit errors detect karta hai — yeh kehta hai "jo bits maine receive kiye woh bheje gaye bits se match karte hain." Ek healthy node ki taraf se bheja gaya logically wrong value perfectly CRC pass karta hai.
Apne fire-alarm message ko highest ID number assign karna use top priority deta hai.
False aur dangerous. Sabse chhota numeric ID jeet ta hai; fire alarm ko 0x001 do, kabhi 0x7FF mat do, kyunki zyada leading dominant (0) bits ise bus par rakhta hai.

Spot the error

"Arbitration ke dauran, ek node jo dominant bhejte waqt dominant padhta hai woh haar gaya hai aur back off karta hai."
Galat. Tum tabhi haarte ho jab tum recessive (1) bhejte ho lekin dominant (0) padhte ho — iska matlab hai koi higher-priority wala bus drive kar raha hai. 0 bhejna aur 0 padhna agreement hai; tum andar rehte ho.
"Ek stuff error 5 identical consecutive bits ke baad declare hota hai."
Galat. Ek stuff bit 5 identical bits ke baad insert kiya jaata hai; stuff error tab fire hota hai jab 6 identical bits dikhen, matlab stuffing rule violate hua (ya deliberately error flag raise kiya gaya).
"Ek form error aur ek CRC error same check hain."
Galat. Ek form error ek fixed-format field (delimiter, EOF) hai jo illegal value rakhta hai; ek CRC error ek checksum mismatch hai. Yeh paanch independent guardians mein se do hain (bit, stuff, CRC, form, ACK), har ek alag failure mode pakadta hai.
"Kisi bhi error par transmitter TEC mein 1 add karta hai aur 8 subtract karke heal karta hai."
Ulta hai. Error par transmitter apne Transmit Error Counter (TEC) mein +8 add karta hai; success par −1 subtract karta hai. Asymmetry offender ko 8× tezi se punish karta hai jitni woh heal karta hai, ek faulty transmitter ko Error-Passive aur Bus-Off ki taraf drive karta hai.
"Ek Error Frame carefully bit-stuffed hai taaki woh normal frame jaisa dikhe."
Galat. Ek active Error Frame 6 dominant bits hai jo deliberately bit stuffing violate karta hai, taaki har node error notice karne par majboor ho aur frame globally discard kare.
"DLC field ek bade payload ko arbitration jeetne deta hai."
Galat. Priority sirf ID field ke dauran decide hoti hai. Data Length Code (DLC) aur Data arbitration settle hone ke baad transmit hote hain aur kabhi affect nahi karte kaun jeetega.
"IDE aur RTR payload bits hain, isliye arbitration ke baad tak matter nahi karte."
Aadha-galat. RTR (Remote Transmission Request) aur IDE (Identifier Extension) arbitration window ke andar/adjacent baithe hain, isliye woh priority decide kar sakte hain — jaise ek data frame (RTR=0, dominant) same ID ke remote frame (RTR=1) ko beat karta hai.

Why questions

Dominant logic 0 kyun define kiya gaya hai na ki logic 1?
Kyunki AND mein ek single 0 result ko 0 force kar deta hai, isliye 0 bhejne wala node open-collector bus ko free mein "jeet ta hai" — arbitration electrical rule se bina kisi referee ke nikal aata hai.
Arbitration lossless kyun ho sakta hai jab Ethernet collisions nahi hote?
CAN par bus value ek live AND hai jo har node bit by bit readback karta hai, isliye loser mid-ID conflict detect karta hai aur hat jaata hai apna data bhejne se pehle bhi; Ethernet collisions tab hi detect karta hai jab dono frames wire par already scramble ho chuke hों.
Extended (29-bit) ID ko arbitration field ke andar apne extra control bits (SRR aur IDE) ki zaroorat kyun hai?
Taaki dono frame types ek wired-AND contest cleanly share kar sakein: SRR (recessive) wahan baitha hai jahan standard RTR tha aur IDE "29-bit follows" mark karta hai, aur unki recessive values guarantee karti hain ki extended frame accidentally same base ID wale standard frame ko out-prioritize nahi karega.
Transmitter TEC mein 8 kyun increment karta hai lekin sirf 1 se decrement karta hai?
Fault confinement achieve karne ke liye — ek node jo errors cause kar raha hai Bus-Off ki taraf bahut tezi se badhta hai jitna woh heal kar sakta hai, isliye ek bad LRU khud ko silence karta hai na ki safety-critical bus ko jam karta hai, jo exactly DO-178C/254 systems require karte hain.
ACK slot named replies ki bajaye collective dominant overwrite kyun use karta hai?
Ek single dominant pull ek bit-time mein bina kisi addressing overhead ke prove karta hai "≥1 healthy receiver exist karta hai," CAN ke message-broadcast model ke saath match karta hai jahan sender ko nahi jaanna ki kaun sun raha hai.
Jab ek node error flag raise karta hai toh saare nodes ek frame kyun discard karte hain?
Consistency — agar kuch nodes ne frame accept kar liya aur kuch ne reject, toh data network ke across diverge ho jaata; globally-visible Error Frame ek uniform "sabhi drop karo aur retransmit karo" decision force karta hai.
CAN ka fixed EOF/delimiter format "form error" kyun check kiya jaata hai?
Un fields ko specific recessive/dominant values rakhni chahiyen, isliye koi bhi deviation ek aise point par corruption reveal karta hai jahan CRC akela localize nahi kar sakta — CRC ke upar ek sasta independent guardian.
Ek Overload Frame exist kyun karta hai agar ek node bas bus idle hone ka wait kar sakta hai?
Ek slow receiver ko ek frame ke theek baad, intermission ke dauran, agle ke shuru hone se pehle ek waqt ki zaroorat ho sakti hai; Overload Frame ise us delay ko actively force karne deta hai na ki ek back-to-back frame miss karne ka risk le jiske liye woh ready nahi hai.
Aerospace mein lower ID naturally zyada urgent messages ke saath correspond kyun karta hai?
Kyunki engineers aise assign karte hain, yeh exploit karte hue ki fewer leading 1s = chhota number = wired-AND jeet ta hai; ARINC 825 jaise conventions ise standardize karte hain taaki ek fire alarm construction se cabin-light status ko outrank kare.

Edge cases

Kya hota hai agar do nodes identical full frames (same ID aur data) transmit karte hain?
Woh arbitration aur payload mein bit-for-bit agree karte hain, isliye koi nahi haarta — dono effectively same frame transmit karte hain aur dono consider karte hain ki frame bhej diya; yahi wajah hai source uniqueness ek design rule hai, accident nahi.
Bus state kya hoti hai jab koi node transmit nahi kar raha?
Idle = recessive (1), kyunki kuch bhi dominant pull na karne par open-collector line high float karti hai; ek falling edge (SOF, dominant 0) listeners ko jagaata hai.
Ek node pichle frame ke baad exactly kab new frame start kar sakta hai?
Tabhi jab EOF plus Intermission (Inter-Frame Space ke 3 recessive bits) pass ho chuke hon aur bus idle ho — intermission ke dauran start karna forbidden hai (woh window Overload Frames ke liye reserved hai).
Kya ek node arbitration jeet sakta hai aur phir bhi apna frame deliver karne mein fail ho sakta hai?
Haan. Woh ID contest jeet ta hai lekin baad mein bit, CRC, form, ya ACK error (kisi ne nahi suna) hit kar sakta hai — arbitration jeetta sirf floor grant karta hai, guaranteed delivery nahi.
Agar ek node apna ID bhejte waqt arbitration ke dauran bus already mid-frame ho toh kya hota hai?
Woh start nahi karta — ek node bus idle (recessive) hone ka aur inter-frame space ka wait karta hai SOF attempt karne se pehle, isliye woh kabhi kisi doosre node ke ongoing frame mein barge nahi karta.
Agar ek node Error-Passive state mein transmit karte waqt ek aur error detect kare toh kya hota hai?
Uska TEC (Transmit Error Counter) badhta rehta hai; jab TEC 255 exceed karta hai woh Bus-Off enter karta hai aur bus drive karna band kar deta hai, fault ko isolate karta hai jabki doosre nodes normally continue karte hain.
Agar sirf REC (Receive Error Counter) chadhe, toh kya ek node Bus-Off reach kar sakta hai?
Nahi. Bus-Off sirf TEC > 255 se trigger hota hai; ek pure witness (high REC) zyada se zyada Error-Passive ban sakta hai, kyunki woh errors cause karne wala nahi hai.
Arbitration aur ACK ke dauran ek bit error deliberately kyun ignore kiya jaata hai?
Un windows mein ek mismatch (recessive bheja, dominant padha) arbitration haarne ya acknowledgment receive karne ka expected signal hai — isliye bit-error check wahan suppress kiya jaata hai false alarms se bachne ke liye.
Recall Page close karne se pehle ek-line self-test

Sent-recessive-read-dominant matlab kya hai, aur yeh error nahi hai kahan? ::: Iska matlab hai "koi higher priority wala drive kar raha hai" — ek normal arbitration loss (ya ek valid ACK), koi error nahi, exactly arbitration aur ACK slots mein.


Connections

  • Parent: 5.5.06 CAN bus — frame format, arbitration, error handling — critical in aerospace (Hinglish)
  • Electrical foundation: Wired-AND logic, Open-collector buses
  • Contrast: CSMA-CD (Ethernet)
  • Integrity: CRC cyclic redundancy check, Bit stuffing and clock recovery
  • Aerospace context: DO-178C / DO-254 aerospace certification, ARINC 825, Real-Time scheduling