5.5.6 · D4Embedded Systems & Real-Time Software

Exercises — CAN bus — frame format, arbitration, error handling — critical in aerospace

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This page is a self-test ladder. Work each problem before opening its solution. Levels climb from L1 Recognition (do you know the words?) up to L5 Mastery (can you design and defend a whole system?). Every solution is spelled out in full so the page teaches even when you get stuck.

Prerequisites you should have from the parent note CAN bus topic: dominant vs recessive bits, Wired-AND logic, arbitration, the frame fields, and the error counters.

Quick reminder of the two words everything rests on:

The single figure below is the visual you will reuse for every arbitration exercise on this page — it is Exercise 2.1 drawn out, and Solution 2.1 refers back to it directly:

Figure — CAN bus — frame format, arbitration, error handling — critical in aerospace

Look at it now: three coloured traces — blue is Node A's bits, orange is Node B's bits, green is the shared bus (the AND of the two). They ride together bit by bit until the red dashed line, where A drives dominant (0) and B drives recessive (1); the green bus goes to 0, B sees the mismatch and drops out, and A alone finishes the frame. Keep this picture in mind for L2.


Level 1 — Recognition

Exercise 1.1

On a CAN bus, three nodes simultaneously transmit the bits , , . What single bit appears on the bus, and is it dominant or recessive?

Recall Solution 1.1

WHAT we do: apply the wired-AND rule bit by bit. Here is the logical AND operator (defined just above the exercises): it gives 1 only when every input is 1, and 0 if any input is 0. WHY: AND returns 0 the moment any input is 0. One node drove dominant (0), so it "pulls the wire down" for everyone. Answer: the bus reads , which is the dominant state.

Exercise 1.2

Which CAN identifier has higher priority: or ?

Recall Solution 1.2

WHAT: compare the two IDs as plain numbers. WHY: in CAN, ==lower numeric ID = higher priority==, because a smaller binary number has its dominant (0) bits earlier, and dominant wins the wired-AND. Answer: (128) has higher priority because .


Level 2 — Application

Exercise 2.1

Node A sends ID 0b10110010101 and Node B sends ID 0b10110100101. Both start together and transmit MSB→LSB. At which bit position (counting the MSB as bit 10 down to bit 0) does arbitration resolve, and which node wins? (This is the scenario drawn in the figure at the top of the page.)

Recall Solution 2.1

WHAT: line the two IDs up and scan left-to-right for the first difference — exactly what the top figure shows in blue (A), orange (B) and green (bus).

bit# 10 9 8 7 6 5 4 3 2 1 0
A 1 0 1 1 0 0 1 0 1 0 1
B 1 0 1 1 0 1 0 0 1 0 1
bus 1 0 1 1 0 0

WHY this bit: bits 10→6 are identical, so both nodes read back exactly what they sent — a tie, keep going. At bit 5 A drives dominant (0) and B drives recessive (1). Wired-AND gives . B sent 1 but reads 0 → mismatch → B loses and becomes a receiver (this is the red dashed line in the figure). Decimal check: and . Answer: arbitration resolves at bit 5; Node A wins (its ID B's ). A's frame is never interrupted; B retransmits later.

Exercise 2.2

A standard CAN data frame carries a 3-byte payload. Ignoring bit stuffing, how many bits are on the wire from SOF through EOF? Use the field table: SOF 1, ID 11, RTR 1, IDE 1, r0 1, DLC 4, Data , CRC 15, CRC-delimiter 1, ACK 1, ACK-delimiter 1, EOF 7.

Recall Solution 2.2

WHAT: add every fixed field, plus the data bits. WHY separate the data term: everything except Data is a fixed-size field; only Data scales with the payload ( bits for bytes). Answer: 68 bits (before bit stuffing and before the 3-bit inter-frame space).


Level 3 — Analysis

Exercise 3.1

A transmitter's Transmit Error Counter starts at TEC = 120 in the Error-Active state. It then commits 2 consecutive transmit errors (no successes between). After these, is the node Error-Active or Error-Passive? Recall: on error TEC += 8; Error-Passive when .

Recall Solution 3.1

WHAT: step the counter twice. WHY the +8: a transmitter causing errors is penalised 8 per error (far faster than the −1 healing on success) so a faulty talker silences itself quickly — this is fault confinement. Check the threshold: after the first error already , so the node is Error-Passive. After the second it sits at TEC = 136, still Error-Passive (not yet Bus-Off, which needs ). Answer: Error-Passive, TEC = 136.

Exercise 3.2

A node sits at TEC = 128 (Error-Passive). It now transmits 12 frames successfully in a row, each success giving . What is its final TEC, and which state is it in?

Recall Solution 3.2

WHAT: decrement 12 times. WHY: each successful transmission subtracts 1, letting a recovered node slowly earn its way back. Check threshold: , so the node is back to Error-Active. Answer: TEC = 116, Error-Active — it healed out of the passive state.

Exercise 3.3

Two error events happen: a transmitter and a receiver each detect one error on the same corrupted frame. If both started at counter value 40, what are their new counters (TEC for the transmitter, REC for the receiver)? Recall: transmitter +8, receiver +1.

Recall Solution 3.3

WHAT: apply each node's rule. WHY the asymmetry: the node causing the error (transmitter) is more likely to be the guilty party, so it climbs 8× faster than a node that merely witnessed the error. This is how the bus isolates the true offender. Answer: transmitter TEC = 48, receiver REC = 41.


Level 4 — Synthesis

Exercise 4.1

You are assigning IDs on an aircraft CAN segment (11-bit standard IDs, so range to ). You have three message types, most-urgent first: engine fire alarm, airspeed reading, cabin light status. Assign one valid ID to each so arbitration always serves them in the correct priority order, and justify the ordering rule.

Recall Solution 4.1

WHAT: urgent messages get the lowest numeric IDs.

Message Suggested ID Numeric
Engine fire alarm 0x001 1
Airspeed reading 0x040 64
Cabin light status 0x7FF 2047

WHY this works: during arbitration all three would transmit their IDs bit by bit. The fire alarm's ID has the most leading dominant (0) bits, so if it ever competes it drives dominant while the others read a mismatch and back off. Ordering check: ✅ matches urgency. Answer: any assignment with is correct; e.g. 0x001, 0x040, 0x7FF.

Exercise 4.2

A designer wants an ACK-error alarm. Explain, step by step, the exact sequence by which a transmitter concludes "nobody heard me," using the ACK-slot mechanism. Then state what error counter change results.

Recall Solution 4.2

WHAT / step sequence:

  1. The transmitter sends the ACK slot as recessive (1) — it deliberately leaves the wire "floating high."
  2. Any receiver that passed the CRC check overwrites that slot with dominant (0).
  3. The transmitter reads the ACK slot back. Dominant (0) → at least one node heard me. Recessive (1) → nobody acknowledged.

WHY it's collective: there is no per-node acknowledgment; a single dominant thumbs-up from any receiver is enough. If the transmitter is the only node on the bus, or all receivers failed CRC, the slot stays recessive → ACK error.

Counter change: an ACK error is a transmit-side failure, so TEC += 8 and the frame is automatically retransmitted. Answer: transmitter reads recessive in the ACK slot ⇒ ACK error ⇒ TEC += 8, retransmit.


Level 5 — Mastery

Exercise 5.1

A faulty transmitter repeatedly fails. It starts at TEC = 231, Error-Passive. Each failed transmission gives +8; assume no successes. How many consecutive failures push it into Bus-Off (defined as )? Give the TEC at the moment it goes Bus-Off.

Recall Solution 5.1

WHAT: find the smallest number of +8 steps that carries 231 past 255. So the smallest integer is . WHY and not 3: after 3 failures TEC = 255, which is not (still Error-Passive, just barely). The 4th failure reaches 263, the first value strictly above 255. Answer: 4 consecutive failures; TEC = 263 at Bus-Off entry.

Exercise 5.2 (design + defend)

Two subsystems share one CAN segment on a DO-178C-certified aircraft: a flight-critical sensor (10 ms period) and a maintenance logger (bursts of large frames). Explain, using CAN mechanisms, why the logger can never delay the sensor beyond one in-progress frame — and compute the worst-case blocking time if the bus runs at 1 Mbit/s and the largest logger frame is (with stuffing) at most 160 bits.

Recall Solution 5.2

WHAT — the priority argument:

  • Give the sensor a low ID (high priority) and the logger a high ID (low priority).
  • CAN arbitration is non-destructive bitwise arbitration: whenever both are ready, the sensor wins at the first differing bit — the logger reads back dominant, loses, and defers. So the logger can never preempt a queued sensor message.

WHAT — the only remaining delay (priority inversion window):

  • The one thing that can delay the sensor is a logger frame already in progress when the sensor becomes ready. CAN cannot interrupt a frame mid-transmission, so the sensor must wait out that single frame. This is the worst-case blocking time.

Compute it: at 1 Mbit/s each bit takes . WHY this is safe: ms is tiny against the sensor's 10 ms period, so the sensor still meets its deadline every cycle (connect this to Real-Time scheduling worst-case-response analysis). Answer: the logger can delay the sensor by at most one in-progress frame = 160 μs; never more, because arbitration is non-destructive and the sensor always wins any fresh contention.


[!recall]- One-line recap of the whole ladder

  • L1: dominant = 0 wins the AND; lower ID = higher priority.
  • L2: arbitration resolves at the first differing bit; a 3-byte frame = 68 bits.
  • L3: transmitter +8 / success −1 gives graded confinement (Active → Passive → Bus-Off).
  • L4: assign urgent = low ID; ACK is a single shared dominant thumbs-up.
  • L5: Bus-Off needs TEC > 255; worst-case blocking = one in-progress frame time.