5.5.6 · D1Embedded Systems & Real-Time Software

Foundations — CAN bus — frame format, arbitration, error handling — critical in aerospace

1,959 words9 min readBack to topic

This page assumes you know nothing. We will name every symbol, draw the picture behind it, and only then let it appear in the main topic. Read top to bottom; each idea is a brick for the next.


1. A "bit" — the smallest thing on the wire

Picture it: a light switch. Down = 0, up = 1. A wire carrying a bit is a switch someone is holding in one position for a slice of time.

Why the topic needs it: CAN sends messages as a long stream of these switch-positions, one after another in time. Before we can talk about frames or IDs, we must agree that the wire, at each instant, is showing exactly one of two symbols.


2. Dominant and recessive — CAN's two special names for 0 and 1

The CAN designers gave the two bit-states nicknames, because on this wire the two states are not equal in power.

Figure — CAN bus — frame format, arbitration, error handling — critical in aerospace

Picture it (figure above): think of a rope everyone holds. Recessive = let the rope float up (that's the relaxed state). Dominant = one strong person yanks it down. One yank beats any number of relaxers — the rope goes down.

Why the topic needs it: this inequality is the entire mechanism of arbitration. A "polite" state (recessive) that anyone can override with a "loud" state (dominant) is what lets nodes compete without a referee.


3. The AND operation — the rule that combines everyone's bit

Now we need the exact rule for what the wire shows when several nodes push different bits at the same instant.

Figure — CAN bus — frame format, arbitration, error handling — critical in aerospace

Picture it (figure above): a row of switches wired in series to a lamp. The lamp lights (result 1) only if every switch is closed (1). Open even one switch (a single 0) and the lamp is dark (0). One 0 kills the whole chain — that is exactly .

Why this exact tool, not OR or XOR? We want a rule where a single node can force the outcome by itself, using the quiet action of "not pushing". AND is the unique operation where one 0 decides everything and the "default" (all 1s) needs unanimous agreement. That maps perfectly onto "one dominant bit wins".

Why the topic needs it: every clever behaviour of CAN (arbitration, the collective ACK, error flags) is just this one formula applied to different fields of the message.


4. Reading numbers written in binary

The message priority is a number, but written as bits. You must be able to read that notation.

Picture it: columns like place-value in decimal, but doubling instead of ×10:

So 0b1011 .

Why the topic needs it: an ID like 0b00010110000 is compared bit by bit from the MSB. Reading MSB→LSB is exactly the order arbitration happens, and leading zeros (which are dominant bits!) are what make a number "win early".


5. Sending bits over time — a bitstream and its clock

Figure — CAN bus — frame format, arbitration, error handling — critical in aerospace

Picture it (figure above): a strip of equal-width boxes moving past a reader. Each box holds one bit. If two people read the strip but disagree on box-width, they read different messages — so a shared sense of timing (a "clock") is essential. See Bit stuffing and clock recovery for how CAN keeps everyone aligned using edges in the stream.

Why the topic needs it: arbitration compares bits at the same instant across nodes. That only works if everyone marches to the same bit-time grid.


6. Comparison and "reading back" — the symbols , , ,

The whole cleverness of a node is: "I sent one thing — did the wire agree?"

Picture it: two sticky notes side by side. if they match, if they differ. For and , imagine a marked ruler with a threshold line; a value sits below-or-on it () or above it ().

Why the topic needs it:

  • A node checks "bit I sent bit on bus?" → if a node sent recessive (1) but reads dominant (0), that mismatch tells it to back off (arbitration) or flags an error.
  • The fault-confinement counters use , , as thresholds. Those symbols are just fences: below the fence = healthy, above = punished.

7. Counters — a number that goes up and down

Picture it: a tally scoreboard. Every foul you cause while talking adds 8 points; every clean moment subtracts 1. Cross point 127 → benched to a quiet mode; cross 255 → you sit out entirely (Bus-Off).

Why the topic needs it: this is how CAN isolates a broken node by itself, without any central authority — the same "no referee" spirit as arbitration, applied to errors.


8. CRC — a checksum, in one sentence

Picture it: a fingerprint of the message. Change any bit and the fingerprint almost certainly changes, so a mismatch shouts "damaged!". Full details live in CRC cyclic redundancy check.

Why the topic needs it: it is one of CAN's five error guardians — the one that catches bits that got flipped by noise after they were sent correctly.


Prerequisite map

Bit = one of two states 0 or 1

Dominant 0 and Recessive 1

Binary numbers MSB to LSB

Bitstream over time and bit-time clock

Logical AND rule

Wired-AND bus value

Lower ID has earlier dominant bits

Non-destructive arbitration

Comparison symbols equal not-equal le gt

Fault confinement counters TEC REC

CRC fingerprint

Error detection

CAN bus topic

This whole page feeds the parent: the CAN bus topic. Related buses that share the wired-AND idea: Open-collector buses, Wired-AND logic. The opposite philosophy (collisions destroy data) is CSMA-CD (Ethernet). Where CAN meets aerospace rules: ARINC 825, DO-178C / DO-254 aerospace certification, and Real-Time scheduling.


Equipment checklist

Self-test: can you answer each before revealing?

What are the two states a single bit can hold, and what symbols do we use?
Two states, written 0 and 1.
Which bit is dominant and which is recessive, in terms of 0/1?
Dominant = 0 (strong, overrides); recessive = 1 (weak, needs unanimous agreement).
State the wired-AND formula for the bus value of bits .
; it is 0 if any bit is 0.
Why is AND the right operation (not OR or XOR)?
Because AND lets a single 0 decide the outcome, matching "one dominant bit wins"; the all-1s default needs unanimity.
Convert 0b1011 to decimal.
.
Reading MSB→LSB, why does a smaller ID win arbitration?
A smaller number has more leading zeros = earlier dominant bits, so it stays on the bus while larger IDs read a mismatch and back off.
What does a node do when it sent recessive (1) but reads dominant (0)?
It recognizes a higher-priority node is talking and backs off (loses arbitration), or in other fields flags a bit error.
What do TEC and REC stand for, and what does += 8 mean?
Transmit/Receive Error Counter; += 8 means add 8 to that counter.
In one sentence, what does a CRC do?
It is a fingerprint of the message; a mismatch between sent and recomputed CRC signals corruption.
Why must all nodes share a bit-time clock?
So they compare bits at the same instant; misaligned timing reads a shifted, wrong bitstream.