CAN bus — frame format, arbitration, error handling — critical in aerospace: Foundations

5.5.6 · D1 · Coding › Embedded Systems & Real-Time Software › CAN bus — frame format, arbitration, error handling — critic

Yeh page assume karta hai ki aap kuch nahi jaante. Hum har symbol ko naam denge, uske peeche ki picture banaenge, aur tabhi use main topic mein aane denge. Upar se neeche padho; har idea agli ke liye ek eent hai.

1. Ek "bit" — wire par sabse chhoti cheez

Ise picture karo: ek light switch. Neeche = 0, upar = 1. Ek bit carry karne wali wire ek aisi switch hai jo koi ek time slice ke liye ek position mein pakde hua hai.

Topic ko yeh kyun chahiye: CAN messages ko in switch-positions ki ek lambi stream ke roop mein bhejta hai, ek ke baad ek time mein. Frames ya IDs ki baat karne se pehle, hum maan lete hain ki wire, har ek instant par, do symbols mein se bilkul ek dikhaa rahi hai.

2. Dominant aur recessive — CAN ke 0 aur 1 ke liye do khaas naam

CAN designers ne do bit-states ko nicknames diye, kyunki is wire par dono states power mein equal nahi hain.

Figure — CAN bus — frame format, arbitration, error handling — critical in aerospace

Ise picture karo (upar ki figure): socho ek rassi jo sab pakde hue hain. Recessive = rassi ko upar float karne do (yeh relaxed state hai). Dominant = ek strong aadmi ise neeche kheeche. Ek khichav kitne bhi relaxers ko beat kar deta hai — rassi neeche jaati hai.

Topic ko yeh kyun chahiye: yeh inequality arbitration ka poora mechanism hai. Ek "polite" state (recessive) jise koi bhi ek "loud" state (dominant) se override kar sake, yehi nodes ko bina referee ke compete karne deta hai.

3. AND operation — woh rule jo sab ka bit combine karta hai

Ab hume exact rule chahiye ki wire kya dikhati hai jab kai nodes ek hi instant par alag-alag bits push karte hain.

$0 \land 0 = 0, 0 \land 1 = 0, 1 \land 0 = 0, 1 \land 1 = 1$

Ise picture karo (upar ki figure): switches ki ek row ek lamp ke saath series mein wired. Lamp jalti hai (result 1) tabhi jab har switch closed (1) ho. Ek bhi switch kholo (ek akela 0) aur lamp dark hai (0). Ek 0 poori chain ko khatam kar deta hai — yahi bilkul $\land$ hai.

Yeh exact tool kyun, OR ya XOR kyun nahi? Hum ek aisi rule chahte hain jahan ek akela node khud hi outcome force kar sake, "not pushing" ki quiet action use karke. AND ek unique operation hai jahan ek 0 sab decide karta hai aur "default" (sab 1s) ke liye unanimous agreement chahiye. Yeh "ek dominant bit jeetta hai" par perfectly map hota hai.

Topic ko yeh kyun chahiye: CAN ka har clever behaviour (arbitration, collective ACK, error flags) bas yahi ek formula hai jo message ke alag-alag fields par apply hota hai.

4. Binary mein likhe numbers padhna

Message priority ek number hai, lekin bits mein likha hua. Aapko woh notation padhni aani chahiye.

Ise picture karo: decimal mein place-value jaisi columns, lekin ×10 ki jagah double hoti hain:

$81402111 = 8 + 0 + 2 + 1 = 11$

Toh 0b1011 $= 11$ .

Topic ko yeh kyun chahiye: 0b00010110000 jaisa ek ID MSB se bit by bit compare kiya jaata hai. MSB→LSB padhna exactly woh order hai jisme arbitration hota hai, aur leading zeros (jo dominant bits hain!) kisi number ko "jaldi jitaate" hain.

5. Bits ko time par bhejna — ek bitstream aur uska clock

Ise picture karo (upar ki figure): equal-width boxes ki ek strip jo ek reader ke paas se guzar rahi hai. Har box mein ek bit hai. Agar do log strip padhen lekin box-width par disagree karen, toh woh alag messages padhenge — isliye timing ka ek shared sense (ek "clock") zaroori hai. Dekho Bit stuffing and clock recovery ke liye ki CAN sab ko stream mein edges use karke aligned kaise rakhta hai.

Topic ko yeh kyun chahiye: arbitration bits ko nodes mein ek hi instant par compare karta hai. Yeh tabhi kaam karta hai jab sab ek hi bit-time grid par chalein.

6. Comparison aur "reading back" — symbols $=$ , $\neq =$ , $\leq$ , $>$

Ek node ki poori cleverness yeh hai: "Maine ek cheez bheji — kya wire ne agree kiya?"

Ise picture karo: do sticky notes side by side. $=$ agar match karein, $\neq =$ agar differ karein. $\leq$ aur $>$ ke liye, socho ek marked ruler ek threshold line ke saath; ek value us par ya neeche baithe ( $\leq$ ) ya uske upar ( $>$ ).

Topic ko yeh kyun chahiye:

Ek node check karta hai "bit jo maine bheji $\neq =$ bit on bus?" → agar node ne recessive (1) bheja lekin dominant (0) padha, toh woh mismatch use back off karne ko kehta hai (arbitration) ya error flag karta hai.
Fault-confinement counters $\leq 127$ , $> 127$ , $> 255$ thresholds use karte hain. Woh symbols bas fences hain: fence ke neeche = healthy, upar = punished.

7. Counters — ek number jo upar-neeche jaata hai

Ise picture karo: ek tally scoreboard. Jab aap baat karte waqt har foul karo toh 8 points add hote hain; har clean moment 1 ghatata hai. 127 cross karo → quiet mode mein bench; 255 cross karo → aap bilkul bahar (Bus-Off).

Topic ko yeh kyun chahiye: yahi hai kaise CAN ek toote node ko khud hi isolate karta hai, bina kisi central authority ke — wohi "no referee" spirit arbitration jaisi, lekin errors par apply hoti hai.

8. CRC — ek sentence mein checksum

Ise picture karo: message ka ek fingerprint. Koi bhi bit change karo aur fingerprint almost certainly change ho jaata hai, toh mismatch chillata hai "damaged!". Poori details CRC cyclic redundancy check mein hain.

Topic ko yeh kyun chahiye: yeh CAN ke paanch error guardians mein se ek hai — woh jo bits pakad ta hai jo noise se flip ho gaye the sahi bheje jaane ke baad.

Prerequisite map

Yeh poora page parent ko feed karta hai: the CAN bus topic. Related buses jo wired-AND idea share karte hain: Open-collector buses, Wired-AND logic. Opposite philosophy (collisions data destroy kar dete hain) CSMA-CD (Ethernet) hai. Jahan CAN aerospace rules se milta hai: ARINC 825, DO-178C / DO-254 aerospace certification, aur Real-Time scheduling.

Equipment checklist

Self-test: kya aap reveal karne se pehle har jawab de sakte ho?

Ek single bit kaun si do states hold kar sakta hai, aur hum kaunse symbols use karte hain?

Do states, likhe 0 aur 1.

0/1 ke terms mein kaun sa bit dominant hai aur kaun sa recessive?

Dominant = 0 (strong, override karta hai); recessive = 1 (weak, unanimous agreement chahiye).

Bits

b_{1}, \dots, b_{n}

ke liye bus value ka wired-AND formula batao.

bus = b_{1} \land b_{2} \land \dots \land b_{n}

; yeh 0 hai agar koi bhi bit 0 ho.

AND sahi operation kyun hai (OR ya XOR kyun nahi)?

Kyunki AND ek akele 0 ko outcome decide karne deta hai, "ek dominant bit jeetta hai" se match karta hai; all-1s default ke liye unanimity chahiye.

0b1011 ko decimal mein convert karo.

8 + 0 + 2 + 1 = 11

MSB→LSB padhte waqt, chhota ID arbitration kyun jeetta hai?

Chhote number mein zyada leading zeros hote hain = pehle dominant bits, toh yeh bus par raha jab bade IDs mismatch padhte aur back off karte hain.

Ek node kya karta hai jab usne recessive (1) bheja lekin dominant (0) padha?

Yeh recognize karta hai ki ek higher-priority node baat kar raha hai aur back off karta hai (arbitration haar jaata hai), ya doosre fields mein bit error flag karta hai.

TEC aur REC kya stand karte hain, aur += 8 ka kya matlab hai?

Transmit/Receive Error Counter; += 8 matlab us counter mein 8 add karo.

Ek sentence mein, CRC kya karta hai?

Yeh message ka ek fingerprint hai; bheji gayi aur recomputed CRC ke beech mismatch corruption signal karta hai.

Sab nodes bit-time clock share kyun karte hain?

Taaki woh ek hi instant par bits compare karein; misaligned timing ek shifted, galat bitstream padhti hai.