Communication interfaces — UART, SPI, I2C (master - slave), CAN bus: Worked examples

5.5.5 · D3 · Coding › Embedded Systems & Real-Time Software › Communication interfaces — UART, SPI, I2C (master - slave),

The scenario matrix

Har row ek case class hai — ek aisi situation jो topic throw kar sakta hai. Har ek ko neeche kam se kam ek worked example (WE#) cover karta hai.

Cell	Case class	Kaun sa protocol	Covered by
A	Normal timing — ek byte bhejna, duration nikalna	UART	WE1
B	Degenerate input — clock mismatch tolerance ke limit par	UART	WE2
C	Full-duplex swap — likhte waqt padhna (ring of shift registers)	SPI	WE3
D	Wire-count scaling — N slaves, many-slave limit	SPI	WE4
E	Resistor sizing do bounds ke beech (upper & lower)	I2C	WE5
F	Zero / no-device case — NACK, koi jawab nahi deta	I2C	WE6
G	Wired-AND arbitration — do IDs collide karte hain, kaun jeetha hai	CAN	WE7
H	Limiting value — full speed par sabse lamba bus	CAN	WE8
I	Real-world word problem — ek system mein sensor budget	mixed	WE9
J	Exam-style twist — "obvious" answer galat hai	I2C/SPI	WE10

WE1 — UART: ek byte bhejna kitna time leta hai? (Cell A)

Bits count karo. 8N1 frame = 1 start + 8 data + 1 stop = 10 bits total, jinmein se 8 payload hain. Yeh step kyun? Line sirf voltage-vs-time carry karti hai; start aur stop bits wire par real time hain, isliye duration mein count hote hain.
Ek bit ki duration nikalo. Baud $B$ = bits/second, toh $t_{bi t} = 1/ B = 1/19200 = 52.08 μ s$ . Yeh step kyun? UART mein sab kuch bit-times mein measure hota hai; measure karne se pehle ruler chahiye.
Total frame time. $10 \times 52.08 μ s = 520.8 μ s$ . Yeh step kyun? Bits back-to-back bheje jaate hain, toh bas count ko ruler se multiply karo.
Waste fraction. Framing bits = 2 of 10 = $0.20 = 20%$ . Yeh step kyun? Effective throughput hamesha baud number se kam hoti hai — yahi reason hai.

Verify: $520.8 μ s \times 19200 = 10.0$ bit-slots ✓. Value 'K' ka timing ke liye koi matlab nahi (ek 0x00 byte utna hi time leta hai) — timing sirf bit count par depend karti hai, bit values par nahi. Units: $bits \div (bits/s) = s$ ✓.

Dekhein Baud rate & clock generation (timers/PLL) iske liye ki ek timer/PLL actually 19200 edges per second kaise produce karta hai.

WE2 — UART: tolerance edge par clock mismatch (Cell B — degenerate/limit)

Figure — Communication interfaces — UART, SPI, I2C (master - slave), CAN bus

Figure s01: bit-times mein ek time axis. White circles ideal mid-bit sample points mark karte hain (ek per bit, exactly ek bit apart spaced). Amber squares dikhate hain ki 4% fast clock wala receiver actually kahan sample karta hai — har square apne circle ke thoda left mein baitha hai, aur gap bit by bit badhta hai. Last (STOP) bit par amber annotation dikhata hai ki drift 0.38 bit tak pahunch gayi hai, jo 0.5-bit half-window ke andar hai, toh byte sahi padha jaata hai.

Sabse kharab sample locate karo. Receiver mid-bit sample karta hai, toh STOP bit (10th bit) ko start edge se 9.5 bit-times baad sample kiya jaata hai. Figure mein, amber square har bit par apne white circle se aur door drift karta hai — aakhri wala sabse zyada drift hai. Yeh step kyun? Error accumulate hoti hai; aakhri sample mein sabse zyada drift hoti hai, isliye woh pehle fail hota hai.
Drift accumulate karo. Drift fraction $ε = 0.04$ ke saath, us sample par timing error hai $9.5 ε t_{bi t} = 9.5 \times 0.04 = 0.38$ bit-times. Yeh step kyun? Har bit $ε t_{bi t}$ slip add karta hai; $n$ bits ke baad yeh $n ε t_{bi t}$ ho jaata hai.
Margin se compare karo. Sample point zyada se zyada half a bit (0.5) slip kar sakta hai galat window mein jaane se pehle. Kyunki $0.38 < 0.5$ , sample sahi bit ke andar hi land karta hai → byte sahi padha gaya (figure mein yahi shaded margin hai). Yeh step kyun? Mid-bit sampling $\pm 0.5$ bit safety window deta hai; yahi poori sampling strategy ka point hai.
Breaking point nikalo. Solve karo $9.5 ε = 0.5 \Rightarrow ε = 0.0526 = 5.26%$ . Yeh step kyun? Yeh limiting value hai — woh degenerate case jahan 4% fatal ho jaata.

Verify: Margin baki = $0.5 - 0.38 = 0.12$ bit-times ✓. Bilkul $ε = 5.26%$ par drift $0.5$ ke equal hai (edge par) ✓. Sanity: bada $n$ (jaise 2 stop bits, zyada data bits) → chhoti tolerance, jo intuition se match karta hai ki lambe frames zyada drift karte hain.

WE3 — SPI: full-duplex byte swap (Cell C)

Figure s02: master ka 8-bit shift register (left, 0xA5 hold karta hua) aur slave ka (right, 0x3C hold karta hua) do boxes ki tarah draw kiye gaye hain ek ring mein wire kiye hue — MOSI bits master→slave top se le jaata hai, MISO bits slave→master bottom se, aur SCLK (cyan) master se slave tak jaata hai. Neeche, "after 8 clocks" state dikhata hai ki boxes ne contents exchange kar liye: master = 0x3C, slave = 0xA5.

Ring dekho. MOSI master→slave feed karta hai, MISO slave→master feed karta hai. Do 8-bit Shift registers ek 16-bit loop banate hain (figure ke top mein). Yeh step kyun? SPI mein koi memory-copy nahi hoti; yeh sirf flip-flops ki physical ring rotate karta hai.
Har clock = ek shift. 8 rising edges (Mode 0) mein se har ek par, master apna current MSB MOSI se bahar push karta hai aur saath hi MISO se slave ka MSB latch karta hai. Yeh step kyun? Yahi simultaneity exactly "full-duplex" ka matlab hai — ek edge dono taraf data move karti hai. MSB-first matlab leftmost bit pehle jaata hai.
8 edges ke baad. Master ke original sare 8 bits slave mein aa gaye, aur vice-versa. Master ab 0x3C hold karta hai, slave 0xA5 (figure ke bottom mein). Yeh step kyun? 8 shifts = ek full byte swap; registers ne apne contents exchange kar liye.

Verify: $master_{final} = 0 x 3 C = 60$ , $slave_{final} = 0 x A 5 = 165$ . XOR-swap identity: swapping apna inverse hai, toh 8 aur clocks 0xA5/0x3C restore kar denge ✓. Koi bit create ya destroy nahi hua: $0 x A 5 \oplus 0 x 3 C$ pehle = baad mein (ek pure permutation ka invariant) ✓.

WE4 — SPI: N slaves ke liye kitne wires? (Cell D — scaling / limit)

Fixed bus wires. MOSI, MISO, SCLK sare slaves mein shared hain → 3 pins, N ki parwah kiye bina. Yeh step kyun? Ye broadcast lines hain; sirf selected slave hi sunta/drives MISO karta hai.
Per-slave selects. SPI mein koi addressing nahi hai, isliye har slave ko apni SS line chahiye → $N$ pins. Yeh step kyun? Master device select karne ka sirf ek hi tarika hai: us device ki apni SS low pull karna (parent ka [!mistake] dekho).
Total. $3 + N = 3 + 6 = 9$ pins. Yeh step kyun? Wires = shared bus + ek select each.
I2C comparison. I2C SDA + SCL = 2 wires use karta hai sare 6 devices ke liye, kyunki yeh pin se nahi balki 7-bit number se address karta hai. Yeh step kyun? Yahi fundamental SPI-vs-I2C trade hai: SPI speed paane ke liye pins kharach karta hai; I2C pins bachane ke liye protocol overhead kharach karta hai.

Verify: SPI $= 3 + 6 = 9$ ; I2C $= 2$ (N mein constant). Limiting behaviour: jaise $N \to \infty$ , SPI pins $\to \infty$ lekin I2C 2 rehta hai ✓ — exactly isliye I2C device count par jeetha hai. Dekhein Serial vs Parallel communication ki 9 serial pins bhi parallel bus se kyon behtar hai.

WE5 — I2C: do bounds ke beech pull-up resistor (Cell E)

Upper bound (speed). Line HIGH threshold ki taraf RC ki tarah rise karti hai; rise time $t_{r} \approx 0.85 R_{p} C_{b}$ . $R_{p}$ ke liye solve karo: $R_{p} < \frac{t _{r, ma x}}{0.85 C _{b}} = \frac{300 \times 1 0 ^{- 9}}{0.85 \times 200 \times 1 0 ^{- 12}} \approx 1765 Ω.$ Yeh step kyun? Bahut bada resistor → slow edge → line next clock se pehle HIGH nahi pahunchti → 400 kHz par bus fail.
Lower bound (sink current). Jab koi device LOW pull karti hai, current $(V_{cc} - V_{O L}) / R_{p}$ itni nahi honi chahiye jo woh sink kar sake: $R_{p} > \frac{V _{cc} - V _{O L}}{I _{O L, ma x}} = \frac{3.3 - 0.4}{3 \times 1 0 ^{- 3}} = 966.7 Ω.$ Yeh step kyun? Bahut chhota resistor → bahut zyada current → open-drain transistor line ko $V_{O L}$ se neeche nahi rakh sakta → "0" ek weak "1" ki tarah padhta hai.
Window. $967 Ω < R_{p} < 1765 Ω$ . Ek common choice jaise $1.5 k Ω$ aaram se andar fit hoti hai. Yeh step kyun? Aap do bounds ke beech rehte hain — yahi poora design rule hai.

Verify: $R_{p} = 1500 Ω$ par: rise $t_{r} = 0.85 \times 1500 \times 200 pF = 255 ns < 300$ ✓; sink current $= (3.3 - 0.4) /1500 = 1.93 mA < 3 mA$ ✓. Donon bounds satisfied. Yeh wired-AND behaviour Wired-AND logic in action hai.

WE6 — I2C: koi jawab nahi deta (NACK / zero-device case) (Cell F — degenerate)

Address byte banao. 7-bit address 0x22 top 7 bits mein, R/W = 0 (write) bit0 mein: $byte = (0 x 22 ≪ 1) ∣ 0 = 0 x 44.$ Yeh step kyun? Pehla byte hamesha [7-bit addr][R/W] hota hai; shift address ko R/W bit ke upar le jaata hai.
ACK slot. 8 clocks ke baad, master SDA release karta hai (open-drain → pull-up ke through float HIGH) aur 9th clock deta hai. Present slave SDA LOW pull karta — ACK. Yeh step kyun? HIGH "released/nobody" state hai; sirf real device woh LOW create kar sakti hai jiska matlab "main hoon."
Koi device nahi → SDA 9th clock ke dauran HIGH rehta hai = NACK. Master HIGH padhta hai. Yeh step kyun? Koi pull-down karne wala nahi, toh pull-up jeetha hai → master literally device ki absence dekhta hai.
Master abort karta hai. Woh STOP issue karta hai aur "no ACK / device not found" report karta hai. Yeh step kyun? NACK protocol ka built-in "kya tum wahan ho?" mechanism hai — koi timeout guessing nahi chahiye.

Verify: $(0 x 22 ≪ 1) ∣ 0 = 0 x 44 = 68$ ✓. Agar wahi device read ki jaati, byte $= (0 x 22 ≪ 1) ∣ 1 = 0 x 45 = 69$ ✓. Khaali address par NACK isliye hi bus scanners kaam karte hain: woh 0x00–0x7F har address probe karte hain aur record karte hain kaun ACK karta hai.

WE7 — CAN: do nodes collide karte hain, kaun jeethta hai? (Cell G — wired-AND arbitration)

Definition Wired-AND arbitration (woh bus rule jis par yeh example tikaa hai)

CAN bus par har node ek hi do wires share karta hai aur sirf bus ko dominant state par pull kar sakta hai ya usse recessive state ke liye release kar sakta hai — woh opposite force nahi kar sakta. Toh bus level har node jo drive kar raha hai uska logical AND hota hai: agar koi bhi node dominant 0 drive kare, poora bus 0 padhta hai; bus recessive 1 tab hi padhta hai jab sab nodes release karein. Yeh I2C ki open-drain lines waala wired-AND hi hai. Arbitration isko exploit karta hai: har node apna message ID bit-by-bit transmit karta hai jabki bus sun raha hota hai; jo node recessive 1 bheja lekin dominant 0 padha usse pata chalta hai ki koi aur node lower ID ke saath bol raha hai, aur woh silently back off kar leta hai. Kuch corrupt nahi hota — winner ko kuch notice bhi nahi hota.

Figure s03: 11 bits ki teen aligned rows, b10 (MSB, left) se b0 (LSB, right) tak labelled. Top row (cyan) = P ki ID 0x2C3; middle row (white) = Q ki ID 0x2A0; bottom row (amber) = bus par actually dikhne wala wired-AND result (har bus bit = P-bit AND Q-bit). Ek amber vertical band us pehle column ko highlight karta hai jahan P aur Q differ karte hain; annotation dikhata hai P wahan 1 bhejta hai lekin bus 0 padhta hai, toh P haarta hai aur Q jeethta hai.

Donon IDs binary mein likho (MSB first), 11 bits mein aligned. 11 bits tak pad karte hue aur readability ke liye 3-4-4 mein group karte hue: $0 x 2 C 3 = 01011000011, 0 x 2 A 0 = 0101010 0000.$ Columns ko b10 (leftmost) se b0 (rightmost) label karo, figure se match karte hue. Yeh step kyun? Arbitration bits ko MSB (b10) se ek column at a time compare karta hai, isliye donon IDs ko compare karne se pehle same 11-bit width tak pad karna aur same columns mein line up karna zaroori hai.
Rule yaad karo. Bus wired-AND hai: dominant 0, recessive 1 ko beat karta hai (upar callout mein define kiya). Har node transmit karta hai aur sunta hai; agar 1 bheja lekin 0 padha, woh haara. Yeh step kyun? Yahi parent ka non-destructive arbitration hai — koi bit corrupt nahi hoti, haarne wala bas side ho jaata hai.
Column by column compare karo (figure mein aligned rows). b10 se padhna:
- b10: P=0, Q=0 → same.
- b9: P=1, Q=1 → same.
- b8: P=0, Q=0 → same.
- b7: P=1, Q=1 → same.
- b6: P=1, Q=0 → differ. Bus 0 padhta hai (dominant). P ne 1 bheja lekin 0 padha → P haarta hai; Q jeethta hai bit b6 par. Yeh step kyun? Pehla differing column sab decide karta hai; woh node jiske paas wahan 0 hai (lower ID) chalti rehti hai. Note karo ki differing bit b6 hai, left se 5th column.
Arithmetic se confirm karo. $0 x 2 A 0 = 672 < 0 x 2 C 3 = 707$ , toh lower ID (Q) jeethta hai. ✓ Yeh step kyun? "Lowest ID jeethta hai" aur "MSB-first bits par wired-AND" — dono ek hi baat hain — yeh cross-check isko prove karta hai.

Verify: $0 x 2 A 0 = 672$ , $0 x 2 C 3 = 707$ , aur $672 < 707$ toh Q jeethta hai ✓. Pehla differing bit: $0 x 2 C 3 \oplus 0 x 2 A 0 = 0 x 063$ , highest set bit bit 6 (b6) hai, jahan P ka 1 hai aur Q ka 0 ✓. Q ka message uncorrupted chalta rehta hai — isliye CAN winner ko kabhi retransmit nahi karta. Dekhein Bit stuffing & CRC in CAN frames aur Differential signaling & noise immunity.

WE8 — CAN: full speed par sabse lamba bus (Cell H — limiting value)

Timing rule. Arbitration ke liye door waale node ka dominant bit paas waale node tak pahunchna aur loss-detect ek bit time ke andar hona chahiye — toh round-trip ek bit mein fit hona chahiye: $t_{bi t} \geq 2 t_{p r o p} = 2 \cdot \frac{L}{v} .$ Yeh step kyun? Agar door waale node ka bit is bit ke khatam hone se pehle nahi pahuncha, toh haarne wala detect nahi kar sakta ki woh haara — arbitration toot jaata hai (isliye WE7 ka "listen while you talk" ek bit ke andar poori bus settle hona maangta hai).
1 Mbps par bit time. $t_{bi t} = 1/ (1 0^{6}) = 1 μ s$ . Yeh step kyun? Bit rate fix karta hai ki "listening window" kitni lambi hai; timing rule ko distance mein convert karne se pehle yeh number chahiye.
L ke liye solve karo. Timing rule $t_{bi t} \geq 2 L / v$ ko maximum length ke liye rearrange karo: $L \leq \frac{v t _{bi t}}{2} = \frac{2 \times 1 0 ^{8} \times 1 \times 1 0 ^{- 6}}{2} = 100 m .$ Yeh step kyun? Yeh $L$ ko isolate karta hai — limiting length. Toh maximum ideal bus 100 m hai; real buses 1 Mbps par ~40 m use karte hain jab transceiver aur oscillator delays budget kha lete hain.

Verify: $L = (2 \times 1 0^{8} \cdot 1 0^{- 6}) /2 = 100$ ✓. Inverse trade-off check karo: 500 kbps tak drop karo ( $t_{bi t} = 2 μ s$ ) → $L \leq 200 m$ ✓ — speed aadhi karna reach double kar deta hai, $L \propto t_{bi t}$ relationship se match karta hua.

WE9 — Real-world word problem: mixed-protocol system budget (Cell I)

I2C bit count. START + 3 bytes, har byte = 8 bits + 1 ACK = 9 bits, + STOP. Approx $1 + 3 \times 9 + 1 = 29$ bits. Yeh step kyun? I2C har ACK par ek poora clock spend karta hai — overhead real hai, isliye count karo.
I2C time. 400 kHz par, $t_{bi t} = 1/ (4 \times 1 0^{5}) = 2.5 μ s$ . Total $\approx 29 \times 2.5 = 72.5 μ s$ . Yeh step kyun? UART jaisa hi "count × bit-time" ruler.
SPI bit count & time. 256 bytes × 8 bits = 2048 bits, koi start/stop/ACK overhead nahi. 8 MHz par, $t_{bi t} = 1/ (8 \times 1 0^{6}) = 0.125 μ s$ . Total $= 2048 \times 0.125 = 256 μ s$ . Yeh step kyun? SPI ka zero-overhead + high clock exactly isliye choose kiya jaata hai bulk transfer ke liye.
Compare karo. SPI dump ( $256 μ s$ ) bottleneck hai, ~3.5× I2C read ( $72.5 μ s$ ) se. Yeh step kyun? Design lesson: slow low-pin sensors ke liye I2C lo, high-volume data ke liye SPI — numbers parent ke "killer feature" column ko justify karte hain.

Verify: I2C $\approx 29 \times 2.5 = 72.5 μ s$ ✓; SPI $= 2048 \times 0.125 = 256 μ s$ ✓; ratio $256/72.5 \approx 3.53$ ✓. Interrupts vs Polling thinking use karta hai: us $256 μ s$ SPI burst ke dauran aap typically DMA use karte ho poll karne ki jagah.

WE10 — Exam-style twist: "obvious" answer ek trap hai (Cell J)

SPI select count. SPI ko ek SS per slave chahiye = 3 selects, plus shared MOSI/MISO/SCLK. SPI address jaisi koi cheez nahi hoti — SPI ke liye "3" 3 pins hain, addresses nahi. Yeh step kyun? Trap SPI ki pin-based selection ko I2C ki address-based selection ke saath conflate karta hai; ye alag resources hain.
I2C address count. 3 I2C slaves = 0 extra select pins (sab SDA/SCL share karte hain), bas 3 alag 7-bit addresses usi 2 wires par. Toh "6 resources" bekaaar hai — SPI pins kharach karta hai, I2C address values kharach karta hai. Yeh step kyun? Pins aur addresses add karna apples + oranges hai; exam ka sum ek category error hai.
Address-byte trap. I2C address 0x50 wire par 0x50 nahi hai. Yeh top 7 bits mein occupy karta hai R/W bit appended ke saath: $write byte = (0 x 50 ≪ 1) ∣ 0 = 0 x A 0.$ Yeh step kyun? Classic off-by-one-bit error — datasheet ka "7-bit address" R/W bit OR karne se pehle left shift hona chahiye.
Read byte bhi correct karo. $(0 x 50 ≪ 1) ∣ 1 = 0 x A 1$ . Yeh step kyun? Read vs write sirf bit0 mein differ karte hain, jo shifted address ke neeche baitha hai.

Verify: $(0 x 50 ≪ 1) ∣ 0 = 0 x A 0 = 160$ ✓; $(0 x 50 ≪ 1) ∣ 1 = 0 x A 1 = 161$ ✓. SPI selects $= 3$ (pins), I2C selects $= 0$ (pins) lekin 3 addresses — toh " $6$ resources" ka claim donon counts par galat hai ✓.

Recall Self-test — answers cover karo

UART 8N1 frame bit count ::: 10 bits (1 start + 8 data + 1 stop) 8N1 ke liye worst-case UART clock tolerance ::: lagbhag 5.26% ( $0.5/9.5$ ) SPI ko ek SS per slave kyun chahiye ::: SPI mein koi addressing nahi; master sirf us slave ki apni SS low pull karke device select karta hai I2C address 0x68 write byte ki tarah ::: $(0 x 68 ≪ 1) ∣0 = 0 x D 0$ "NACK" master ko kya bataata hai ::: kisi ne SDA low nahi kiya → us address par koi nahi CAN arbitration winner rule ::: sabse chhota numeric ID (sabse zyada leading dominant 0s wala) non-destructively jeethta hai 1 Mbps par max classic-CAN length (ideal) ::: ~100 m, $L = v t_{bi t} /2$ se