Communication interfaces — UART, SPI, I2C (master - slave), CAN bus: Visual walkthrough

5.5.5 · D2 · Coding › Embedded Systems & Real-Time Software › Communication interfaces — UART, SPI, I2C (master - slave),

Ye parent topic ke CAN section ka central magic hai: non-destructive bitwise arbitration. Hum isse zero se derive karte hain.

Step 1 — Wire par hota kya hai? Do lines, ek difference

KYA. CAN do wires use karta hai, jinhe CANH aur CANL kehte hain. Ek receiver inme se koi ek wire akele nahi padhta. Wo difference padhta hai: $V_{diff} = V_{CANH} - V_{CANL} .$

$V_{CANH}$ ::: "high" wire par voltage, ground ke against measure kiya gaya
$V_{CANL}$ ::: "low" wire par voltage, ground ke against measure kiya gaya
$V_{diff}$ ::: wo ek number jis par receiver ko actually care hai — dono ke beech ka gap

Difference kyun, ek wire kyun nahi? Kyunki noise (ek spark, ek motor) dono wires ko almost identically hit karta hai — wo $V_{CANH}$ aur $V_{CANL}$ dono mein same bump add karta hai. Jab subtract karte ho, wo shared bump cancel ho jaata hai: $(V_{CANH} + n) - (V_{CANL} + n) = V_{CANH} - V_{CANL} .$ Noise term $n$ gayab ho jaata hai. Yahi differential signaling ka poora point hai — pehle wo padho agar ye naya hai.

PICTURE. Neeche: jab noise hit karta hai dono wires saath hiltey hain (upar), lekin unka difference (neeche) clean rehta hai.

Figure — Communication interfaces — UART, SPI, I2C (master - slave), CAN bus

Step 2 — Do named states: dominant aur recessive

KYA. CAN do logic values ko special names deta hai, aur ye symmetric nahi hain:

Ye names matter karte hain: "dominant" literally jeet jaata hai. Ye seedha rakho —

Kaunsa bit value dominant hai?

logic 0

Kaunsa bit value recessive hai?

logic 1

Inhe high/low ki jagah aise kyun name kiya? Kyunki electrical behaviour lopsided hai, bilkul ek open-drain line ki tarah. Ek node dominant state ko sirf force kar sakta hai; recessive hone ke liye wo bas forcing band kar deta hai aur bus ko relax karne deta hai. Isliye agar koi bhi dominant push kare jab baaki sab recessive hon, poori bus dominant ho jaati hai. Recessive kabhi dominant ko override nahi kar sakta.

PICTURE. $V_{diff}$ levels par draw ki gayi dono states, saath mein "kaun ise force kar sakta hai" arrow.

Step 3 — Wired-AND: bus sabhi talkers ka logical AND compute karta hai

KYA. Kaafi nodes ek hi do wires par lagao. Bus level ek rule follow karta hai:

Kyunki dominant = 0, ek bhi dominant (0) AND ko 0 force kar deta hai. Ye exactly Wired-AND logic hai — wahi trick jo I2C SDA par use karta hai.

Electronics mein AND kyun nikalta hai? Step 2 se: ek node sirf dominant(0) ki taraf pull kar sakta hai ya recessive(1) ke liye release kar sakta hai. "Sabne release kiya" — sirf tabhi bus recessive(1) rehti hai. Ek bhi puller → dominant(0). Wo truth table AND hai. Koi bhi chip AND gate nahi run kar raha; wires physically ye karte hain.

PICTURE. Teen nodes, unke bits, aur resulting bus — kisi ke bhi dominant 0 se poori line neeche aa jaati hai.

Step 4 — Key move: har talker bhi sunta hai, bit by bit

KYA. Jab ek node har bit transmit karta hai, wo turant bus ko read-back karta hai aur compare karta hai: $sent bit = ? read-back bit .$

Sirf do outcomes hain:

sent = read-back → Main bus se agree karta hun → aage jaao.
sent recessive(1) lekin read-back dominant(0) → koi stronger line par hai → Main haara, turant transmit karna band karo, sirf sunne mein aa jao.

Note karo teesra case (sent dominant, read recessive) impossible hai: Step 3 se, agar tum dominant bhejo toh bus dominant hi hai. Isliye "haarne" ka ek hi tarika hai — ek 1 bhejo aur 0 suno.

End tak wait kyun nahi karte mismatch ke liye? Kyunki agar tum message khatam hone tak wait karo clash notice karne ke liye, tab tak message already garble ho chuka hoga aur re-send karna padega — ordinary networks yahi karte hain (poll/retry style). CAN har bit ke andar check karta hai, isliye wo kuch corrupt karne se pehle bail out kar sakta hai. Isliye survivor ka message kabhi damage nahi hota.

PICTURE. Compare loop: transmit driver upar, sense line wapas ek comparator mein feed ho rahi hai.

Step 5 — Khelo: do nodes apne IDs race karte hain

KYA. Har CAN message apne identifier (ID) se shuru hota hai, MSB-first bheja jaata hai (ek shift register use karke, most-significant bit pehle). Do nodes ek hi instant par start karte hain:

Node A: ID = 0b0100... (numerically chhota)
Node B: ID = 0b0110...

Bits saath saath chalao. Har position par bus = dono ka AND (Step 3), aur har node compare karta hai (Step 4):

bit #	A bhejta hai	B bhejta hai	bus (AND)	A sunta hai	B sunta hai	verdict
1	0	0	0	0 ✓	0 ✓	tie, jaaro
2	1	1	1	1 ✓	1 ✓	tie, jaaro
3	0	1	0	0 ✓	0 ✗	B yahan haarta hai
4	0	(silent)	0	0 ✓	sun raha hai	A akela

B bit 3 par kyun haarta hai. B ne recessive(1) bheja lekin bus ne dominant(0) read kiya (kyunki A ne 0 bheja). Ye exactly Step 4 se losing condition hai. B turant chup ho jaata hai; A ko pata bhi nahi chala ki koi fight thi — A ne jo bhi bit bheja wo bus se match karta raha.

PICTURE. Dono bit streams stacked, neeche AND'd bus, aur bit 3 par pink "B drops out" marker.

Step 6 — Edge case: identical IDs (ya same node "khud se race kar raha hai")

KYA. Agar do nodes bilkul same ID bhejein, har bit tie ho jaata hai — koi kabhi mismatch nahi sunta, isliye koi drop out nahi karta. Kya ye disaster hai?

Ye theek kyun hai. CAN design se forbid karta hai ki do alag nodes ek hi message ID ek saath bhejein — har message ID ka ek single producer hota hai. ID ke baad ek control field aur data aata hai; agar payloads match ho bhi jaayein, to do frames vaise bhi identical hain, isliye bus ek clean copy carry karta hai. Agar rules violate hue (do producers), mismatch baad mein data field mein surface karega ek error ke roop mein aur CRC/error checks se flag ho jaayega — arbitration layer consistent rehti hai, higher layer bug pakad leti hai.

Degenerate sub-case — all-recessive idle. Agar koi transmit nahi kar raha, sab recessive(1) hain, AND 1 hai, bus idle high-diff-zero par hai. Jo pehla node dominant start-of-frame bit (ek 0) bhejta hai wo otherwise-empty bus ko bina contest ke grab kar leta hai.

PICTURE. Do lanes: (left) identical IDs → koi mismatch nahi, ek clean copy; (right) idle bus, ek node dominant SOF bit se kholti hai.

Step 7 — Edge case: wire ki khud ki speed limit

KYA. "Talk karte hue suno" kaam karne ke liye, read-back usi bit ke andar sach hona chahiye. Far end se dominant bit ko cable ke neeche travel karne aur sense hone mein time lagta hai. Agar ek bit us round-trip se chhoti ho, ek node bit khatam kar sakta hai clash sunne se pehle.

Ye length × speed kyun cap karta hai. Rearrange karo, $L \leq \frac{v t _{bit}}{2}$ . Faster bitrate → chhota $t_{bit}$ → allowed cable chhota. Isliye classic CAN sirf ~40 m tak 1 Mbps chala paata hai, aur lambe buses ko slow down karna padta hai. Arbitration speed ko reach ke liye trade karta hai.

PICTURE. $L$ length ki ek cable; far node se near node ki taraf crawl karta dominant edge; bit window itni wide ki trip contain ho sake.

Ek-picture summary

Ek board par poori derivation: do wires → unka difference noise ko maarta hai → dominant(0) hamesha recessive(1) ko beat karta hai → bus ek wired-AND hai → har node har bit mein bolta bhi hai aur sunta bhi hai → sabse pehle 0 wali ID bina corruption ke jeet jaati hai → aur bit wire ke travel time ke liye kaafi lambi honi chahiye.

Recall Feynman retelling — story ki tarah batao

Socho ek kamre mein bheed hai, aur rule ye hai: jo whisper kare wo silence maana jaata hai, lekin jo bhi taali bajaaye poore kamre ko "taali" pe force kar deta hai. (Taali = dominant 0; whisper/silence = recessive 1.) Ab sab ek number spell karna shuru karte hain, ek symbol per second, 0 ke liye taali bajao aur 1 ke liye chup raho — aur important baat, jab tum taali bajate ya chup rehte ho, tum kamra bhi sun rahe ho. Agar tum chup rehna chahte the (ek 1) lekin taali sunai deti hai, matlab koi chhota number wala abhi bhi maidan mein hai — toh tum politely chup ho jaate ho aur bas suno. Tum haare, lekin tumne unka number kabhi bhi gadbad nahi kiya, kyunki tumhari chuppi ne kuch add nahi kiya. Jo sabse chhota number spell kar raha tha wo bit by bit, perfectly, chalta rehta hai, aur use pata bhi nahi chala ki koi contest tha. Bas ek hi pakad hai: sabko itna paas hona chahiye ki ek taali us second khatam hone se pehle har kaan tak pahunche — isliye ek fast, long CAN bus impossible hai; kamra sirf itna bada ho sakta hai.

One-line version ::: differential wires noise cancel karte hain, wired-AND 0 ko 1 se beat karwata hai, listen-while-you-talk lowest ID ko uncorrupted jeetnay deta hai, aur bit time round-trip se zyada hona chahiye taaki sab samay par sun sakein.