Timers — PWM generation, input capture, output compare: Worked examples

Intuition What this page is for

The parent note built the machinery: a counter CNT that ticks up, an auto-reload ARR that says when to wrap, a compare register CCR that decides pin timing, and a prescaler PSC that slows the clock. Now we drill every kind of problem those four numbers can produce — until no exam question can surprise you.

Before line one, here are the only symbols we use, in plain words:

$f_{c l k}$ — the raw peripheral clock, in Hz (ticks per second) — think "how fast the heart beats".
$P S C$ — prescaler register value. The divider is $(P S C + 1)$ ; why +1? so $P S C = 0$ means divide-by-1, not the impossible divide-by-0.
$f_{t im} = f_{c l k} / (P S C + 1)$ — the slowed tick rate the counter actually sees.
$t_{t i c k} = 1/ f_{t im}$ — how long ONE tick lasts, in seconds.
$A R R$ — top count. The counter visits $0, 1, \dots, A R R$ , which is $(A R R + 1)$ distinct ticks. Why +1? because count $0$ is a real tick too.
$C C R$ — compare threshold. In PWM, pin is HIGH while $C N T < C C R$ .
$D$ — duty cycle, the fraction of each period the pin is HIGH.

The scenario matrix

Every timer problem is one (or a blend) of these cells. Each worked example below is tagged with the cell(s) it covers.

#	Cell (case class)	What makes it tricky	Example
A	Forward design, PWM % — pick PSC/ARR/CCR for a target frequency + duty	choosing PSC to keep ticks tidy	Ex 1
B	Forward design, pulse-width (servo/ESC) — set CCR in µs, not %	duty is irrelevant; width matters	Ex 2
C	Degenerate duty — 0%, 100%, and the off-by-one at the top	$C C R = A R R + 1$ vs $C C R = A R R$	Ex 3
D	Toggle mode — square wave, divide-by-2 subtlety	two toggles = one period	Ex 4
E	Input capture, no wrap — measure a frequency	plain subtraction	Ex 5
F	Input capture, WITH wrap — the negative-difference trap	modulo arithmetic	Ex 6
G	Limiting / resolution — smallest & largest frequency a 16-bit timer can hit	ARR range limits	Ex 7
H	Real-world word problem — dim an LED to a perceived brightness	mapping physical want → registers	Ex 8
I	Exam twist — given a scope reading, reverse-engineer the registers	invert every formula	Ex 9

Figure — Timers — PWM generation, input capture, output compare

Example 1 — Cell A: forward PWM design

Worked example 10 kHz PWM at 30 % duty on a 48 MHz timer clock

Forecast: guess before reading — will ARR be in the hundreds, thousands, or tens of thousands? Will CCR be about a third of ARR?

Given: $f_{c l k} = 48 MHz$ , target $f_{P W M} = 10 kHz$ , target $D = 30%$ .

Pick a tidy tick. Choose $P S C = 47$ so $f_{t im} = 48 M /48 = 1 MHz$ ⇒ $t_{t i c k} = 1 μ s$ . Why this step? 1 µs ticks make every later number readable in plain time units — no calculator needed.
Solve ARR from the period. $f_{P W M} = f_{t im} / (A R R + 1)$ ⇒ $A R R + 1 = 1 0^{6} /1 0^{4} = 100$ ⇒ $A R R = 99$ . Why this step? The period is the whole count $0 \to A R R$ , which is $(A R R + 1)$ ticks; invert the frequency formula.
Solve CCR from duty. $D = C C R / (A R R + 1)$ ⇒ $C C R = 0.30 \times 100 = 30$ . Why this step? Duty is HIGH-ticks over total-ticks; multiply the total by the fraction.

Verify: period $= 100 \times 1 μ s = 100 μ s \Rightarrow f = 1/100 μ s = 10 kHz$ ✓. Duty $= 30/100 = 30%$ ✓. Forecast check: ARR is in the hundreds, CCR is ~a third — matches.

Example 2 — Cell B: pulse-width design (servo)

Worked example ESC arming pulse: 50 Hz frame, 1.0 ms pulse

Forecast: the duty here is $1 ms /20 ms = 5%$ — but do we ever type 5 % anywhere? (No — watch why.)

Given: $f_{c l k} = 72 MHz$ , frame rate $50 Hz$ (period $20 ms$ ), pulse width $1.0 ms$ .

Tidy tick again. $P S C = 71 \Rightarrow f_{t im} = 1 MHz \Rightarrow t_{t i c k} = 1 μ s$ . Why? An ESC/servo cares about the pulse duration in microseconds; 1 µs ticks let us set that duration by literally counting µs.
ARR from frame period. $20 ms = 20000 μ s \Rightarrow A R R + 1 = 20000 \Rightarrow A R R = 19999$ . Why? One counter wrap must equal one 20 ms frame.
CCR = pulse in ticks. $1.0 ms = 1000 μ s \Rightarrow C C R = 1000$ . Why? We set CCR to the desired width, not a percentage — the servo/ESC decodes width, so µs is the natural unit.

Verify: width $= 1000 \times 1 μ s = 1 ms$ ✓. Frame $= 20000 \times 1 μ s = 20 ms = 50 Hz$ ✓. Duty works out to $1000/20000 = 5%$ ✓ — correct but never typed.

Example 3 — Cell C: the degenerate duties (0 %, 100 %)

Worked example Full-off and full-on with ARR = 999

Forecast: to get a truly solid-HIGH pin, is $C C R = 999$ enough, or must it be $1000$ ?

Given: $A R R = 999$ ⇒ total ticks per cycle $= A R R + 1 = 1000$ .

0 % (pin always LOW). Set $C C R = 0$ . The rule "HIGH while $C N T < C C R$ " is never true since $C N T$ starts at $0$ and $0 < 0$ is false. Why this step? It shows the boundary is a strict less-than, so $C C R = 0$ collapses HIGH-time to zero.
Near-100 %. Set $C C R = 999$ . HIGH while $C N T < 999$ , i.e. counts $0..998$ = $999$ ticks. Duty $= 999/1000 = 99.9%$ — a one-tick LOW glitch remains at $C N T = 999$ . Why? Demonstrates the classic off-by-one: $A R R$ is NOT the full-on value.
True 100 %. Set $C C R = 1000 = A R R + 1$ . Now $C N T < 1000$ for all counts $0..999$ ⇒ HIGH every tick. Duty $= 1000/1000 = 100%$ . Why? Only $C C R = A R R + 1$ makes the compare hold for the entire cycle.

Verify: duties are $0/1000 = 0%$ , $999/1000 = 99.9%$ , $1000/1000 = 100%$ ✓. This is exactly the [!mistake] "duty is CCR/ARR" trap from the parent — using $A R R = 999$ as the "100 %" value gives $999/1000$ , which is wrong.

Example 4 — Cell D: toggle mode square wave

Worked example Exact 250 kHz square wave via toggle-on-match

Forecast: in toggle mode each match flips the pin. So to produce a wave at 250 kHz, does the timer need to match at 250 kHz or 500 kHz?

Given: $f_{c l k} = 72 MHz$ , $P S C = 0 \Rightarrow f_{t im} = 72 MHz$ , target $f_{o u t} = 250 kHz$ .

Count toggles per period. One full square wave = one HIGH half + one LOW half = two flips. Why this step? The output frequency is half the match rate, so we must double the target before choosing ARR.
Required match rate. $f_{ma t c h} = 2 f_{o u t} = 500 kHz$ . Why? Each match is one toggle; we need 500k toggles/s to make 250k full cycles/s.
Solve ARR. Matches happen every wrap: $f_{ma t c h} = f_{t im} / (A R R + 1) \Rightarrow A R R + 1 = 72 M /500 k = 144 \Rightarrow A R R = 143$ . Why? Same period formula, but the "period" here is the interval between toggles, not between full waves.

Verify: toggle interval $= 144/72 MHz = 2 μ s$ ; two of them $= 4 μ s$ ⇒ $f_{o u t} = 1/4 μ s = 250 kHz$ ✓.

Example 5 — Cell E: input capture, no overflow

Worked example Measure an unknown clean signal

Forecast: two rising-edge captures $c_{1} = 1500$ , $c_{2} = 4000$ at 1 µs/tick. Is the gap 2.5 ms or 2500 µs? (Trick: they're the same!)

Given: $f_{t im} = 1 MHz$ ( $t_{t i c k} = 1 μ s$ ), $A R R = 65535$ , $c_{1} = 1500$ , $c_{2} = 4000$ . No wrap (since $c_{2} > c_{1}$ and the counter is huge).

Elapsed ticks. $Δ = c_{2} - c_{1} = 4000 - 1500 = 2500$ . Why this step? Input capture snapshots CNT at each edge; the difference IS the elapsed count — no software delay.
Convert to time. $T_{s i g na l} = Δ t_{t i c k} = 2500 \times 1 μ s = 2500 μ s = 2.5 ms$ . Why? Each tick is a known 1 µs, so ticks map straight to microseconds.
Invert for frequency. $f_{s i g na l} = 1/ T_{s i g na l} = 1/2.5 ms = 400 Hz$ . Why? Frequency is the reciprocal of the period we just measured.

Verify: $1/ (2500 \times 1 0^{- 6} s) = 400 Hz$ ✓, and $Δ = 2500 < 65536$ confirms no wrap ✓.

Example 6 — Cell F: input capture ACROSS an overflow

Worked example The negative-difference trap

Forecast: $c_{1} = 64000$ , $c_{2} = 1500$ , $A R R = 65535$ . Raw subtraction gives $- 62500$ . Is the real gap therefore negative time (impossible), or did the counter wrap once?

Given: $f_{t im} = 1 MHz$ , $A R R = 65535$ ⇒ modulus $= A R R + 1 = 65536$ , $c_{1} = 64000$ , $c_{2} = 1500$ .

Spot the wrap. $c_{2} < c_{1}$ even though time moved forward ⇒ the counter overflowed between edges. Why this step? A forward time gap can never give a smaller count unless the counter reset to 0 in between.
Apply modulo. $Δ = (c_{2} - c_{1}) mod (A R R + 1) = (1500 - 64000) mod 65536 = 65536 - 62500 = 3036$ . Why? Adding one full modulus $65536$ "undoes" the single wrap, restoring the true forward count.
Convert. $T_{s i g na l} = 3036 \times 1 μ s = 3036 μ s \Rightarrow f_{s i g na l} = 1/3036 μ s \approx 329.4 Hz$ . Why? Same tick→time→frequency chain as Example 5, now on the corrected $Δ$ .

Verify: $65536 - 62500 = 3036$ ✓; $1/ (3036 \times 1 0^{- 6}) \approx 329.38 Hz$ ✓. Ignoring the mod would have crashed the math with a negative period.

Example 7 — Cell G: limiting frequencies of a 16-bit timer

Worked example Slowest and fastest PWM with a 16-bit ARR at 72 MHz

Forecast: with $P S C = 0$ , guess the highest PWM frequency (limited by the smallest usable ARR) and the lowest (limited by max ARR = 65535).

Given: $f_{c l k} = 72 MHz$ , 16-bit timer ⇒ $A R R \in [1, 65535]$ (need $\geq 2$ ticks to make a wave), $P S C = 0$ for the extreme high end.

Fastest PWM. Smallest wave uses $A R R = 1$ ⇒ $A R R + 1 = 2$ ⇒ $f_{P W M} = 72 M /2 = 36 MHz$ . Why this step? Fewer ticks per cycle = higher frequency; $A R R = 1$ (2 ticks) is the coarsest but fastest square wave, though duty resolution is only 0 %/50 %/100 %.
Lowest PWM (still PSC=0). Largest $A R R = 65535$ ⇒ $A R R + 1 = 65536$ ⇒ $f_{P W M} = 72 M /65536 \approx 1098.6 Hz$ . Why? Max ARR stretches the period as far as one 16-bit counter allows before you must also raise PSC.
Go even slower with PSC. To reach, say, ~1 Hz you need $(P S C + 1) (A R R + 1) = 72 M$ . With $A R R = 65535$ : $P S C + 1 = 72 M /65536 \approx 1098.6 \Rightarrow P S C = 1098$ gives $f \approx 1.0006 Hz$ . Why? Two dividers multiply, so PSC extends the range the 16-bit ARR alone can't.

Verify: $72 M /2 = 36 MHz$ ✓; $72 M /65536 \approx 1098.63 Hz$ ✓; $72 M / ((1098 + 1) \cdot 65536) \approx 1.0006 Hz$ ✓.

Example 8 — Cell H: real-world word problem (LED dimming)

Worked example "Make this status LED look 20 % bright, flicker-free."

Forecast: the eye fuses flicker above ~100 Hz. Should we pick a PWM frequency of 20 Hz, 200 Hz, or 20 kHz? And does "20 % bright" translate to duty directly?

Given: $f_{c l k} = 8 MHz$ (a small MCU), want no visible flicker, perceived brightness ≈ 20 %.

Choose a flicker-free frequency. Pick $f_{P W M} = 1 kHz$ (well above the ~100 Hz fusion limit, easy on the eye). Why this step? Below ~100 Hz the LED visibly blinks; 1 kHz guarantees smooth dimming.
Tidy tick + ARR. $P S C = 7 \Rightarrow f_{t im} = 8 M /8 = 1 MHz$ (1 µs). $A R R + 1 = 1 M /1 k = 1000 \Rightarrow A R R = 999$ . Why? Reuse the 1 MHz trick, then invert the period formula for ARR.
Duty for 20 %. For coarse brightness we treat perceived ≈ duty: $C C R = 0.20 \times 1000 = 200$ . Why? Average LED current ∝ duty, so 20 % duty gives roughly 20 % average current (real eyes are gamma-nonlinear, but this is the standard first-order mapping).

Verify: $f = 1 M /1000 = 1 kHz$ (flicker-free) ✓; duty $= 200/1000 = 20%$ ✓.

Example 9 — Cell I: exam twist (reverse-engineer from a scope)

Worked example A scope shows a 4 kHz signal HIGH for 75 µs. Find ARR and CCR.

Forecast: they gave you time on screen, not registers. Which formula do you invert first — period or duty?

Given: $f_{c l k} = 64 MHz$ , observed $f_{P W M} = 4 kHz$ , observed HIGH time $= 75 μ s$ . You choose $P S C$ .

Pick tick, find ARR. $P S C = 63 \Rightarrow f_{t im} = 64 M /64 = 1 MHz$ (1 µs). Period $= 1/4 kHz = 250 μ s \Rightarrow A R R + 1 = 250 \Rightarrow A R R = 249$ . Why this step? Invert $f_{P W M} = f_{t im} / (A R R + 1)$ ; the observed period gives the total tick count.
HIGH time → CCR directly. HIGH lasts $75 μ s = 75$ ticks ⇒ $C C R = 75$ . Why? With 1 µs ticks, HIGH-microseconds equal HIGH-ticks equal CCR.
Cross-check duty. $D = C C R / (A R R + 1) = 75/250 = 30%$ , and indeed $75 μ s /250 μ s = 30%$ . Why? Two independent routes to the same duty confirm the registers are consistent.

Verify: $f_{t im} / (A R R + 1) = 1 M /250 = 4 kHz$ ✓; HIGH $= 75 \times 1 μ s = 75 μ s$ ✓; duty $= 75/250 = 30%$ ✓.

Parent topic (Hinglish) — the machinery these examples exercise.
Clock Tree and Prescalers — where $f_{c l k}$ and the tidy-tick choices come from.
GPIO and Alternate Functions — the pin every PWM/toggle example drives.
Interrupts and NVIC — overflow-counting for the Cell F wrap case.
Servo and ESC Control — Example 2's pulse-width interpretation.
Motor Control and H-Bridges — Example 1 & 8 style duty control at speed.
Encoder Mode — a capture cousin for the curious.

Worked examples — Timers — PWM generation, input capture, output compare