Timers — PWM generation, input capture, output compare: Worked examples

5.5.3 · D3 · Coding › Embedded Systems & Real-Time Software › Timers — PWM generation, input capture, output compare

Intuition Ye page kis liye hai

Parent note ne machinery build ki thi: ek counter CNT jo upar tick karta hai, ek auto-reload ARR jo batata hai kab wrap karna hai, ek compare register CCR jo pin timing decide karta hai, aur ek prescaler PSC jo clock ko slow karta hai. Ab hum har tarah ke problem ko drill karenge jo ye char numbers produce kar sakte hain — tab tak, jab tak koi bhi exam question tumhe surprise na kar sake.

Pehli line se pehle, ye sirf wahi symbols hain jo hum use karte hain, plain words mein:

$f_{c l k}$ — raw peripheral clock, Hz mein (ticks per second) — socho "dil kitni tezi se dhakta hai".
$P S C$ — prescaler register value. Divider hai $(P S C + 1)$ ; +1 kyun? taaki $P S C = 0$ ka matlab divide-by-1 ho, na ki impossible divide-by-0.
$f_{t im} = f_{c l k} / (P S C + 1)$ — slowed tick rate jo counter actually dekhta hai.
$t_{t i c k} = 1/ f_{t im}$ — ek akela tick kitne seconds ka hota hai.
$A R R$ — top count. Counter $0, 1, \dots, A R R$ visit karta hai, jo hai $(A R R + 1)$ distinct ticks. +1 kyun? kyunki count $0$ bhi ek real tick hai.
$C C R$ — compare threshold. PWM mein, pin HIGH rehti hai jab $C N T < C C R$ .
$D$ — duty cycle, har period ka wo fraction jitni der pin HIGH rehti hai.

Scenario matrix

Har timer problem in cells mein se ek (ya inka blend) hoti hai. Neeche har worked example tagged hai un cell(s) ke saath jo wo cover karta hai.

#	Cell (case class)	Kya tricky hai	Example
A	Forward design, PWM % — target frequency + duty ke liye PSC/ARR/CCR choose karo	PSC choose karna taaki ticks tidy rahein	Ex 1
B	Forward design, pulse-width (servo/ESC) — CCR ko µs mein set karo, % mein nahi	duty irrelevant hai; width matter karta hai	Ex 2
C	Degenerate duty — 0%, 100%, aur top par off-by-one	$C C R = A R R + 1$ vs $C C R = A R R$	Ex 3
D	Toggle mode — square wave, divide-by-2 subtlety	do toggles = ek period	Ex 4
E	Input capture, no wrap — frequency measure karo	plain subtraction	Ex 5
F	Input capture, WITH wrap — negative-difference trap	modulo arithmetic	Ex 6
G	Limiting / resolution — 16-bit timer ki smallest & largest frequency	ARR range limits	Ex 7
H	Real-world word problem — LED ko perceived brightness par dim karo	physical want ko registers se map karna	Ex 8
I	Exam twist — scope reading dekhke registers reverse-engineer karo	har formula ko invert karo	Ex 9

Figure — Timers — PWM generation, input capture, output compare

Example 1 — Cell A: forward PWM design

Worked example 48 MHz timer clock par 10 kHz PWM at 30% duty

Forecast: padhne se pehle guess karo — ARR hundreds mein hoga, thousands mein, ya tens of thousands mein? Kya CCR ARR ka roughly ek-third hoga?

Given: $f_{c l k} = 48 MHz$ , target $f_{P W M} = 10 kHz$ , target $D = 30%$ .

Tidy tick choose karo. $P S C = 47$ choose karo taaki $f_{t im} = 48 M /48 = 1 MHz$ ⇒ $t_{t i c k} = 1 μ s$ . Ye step kyun? 1 µs ticks baad ke har number ko plain time units mein readable banate hain — koi calculator nahi chahiye.
Period se ARR solve karo. $f_{P W M} = f_{t im} / (A R R + 1)$ ⇒ $A R R + 1 = 1 0^{6} /1 0^{4} = 100$ ⇒ $A R R = 99$ . Ye step kyun? Period hai pura count $0 \to A R R$ , jo hai $(A R R + 1)$ ticks; frequency formula ko invert karo.
Duty se CCR solve karo. $D = C C R / (A R R + 1)$ ⇒ $C C R = 0.30 \times 100 = 30$ . Ye step kyun? Duty hai HIGH-ticks over total-ticks; total ko fraction se multiply karo.

Verify: period $= 100 \times 1 μ s = 100 μ s \Rightarrow f = 1/100 μ s = 10 kHz$ ✓. Duty $= 30/100 = 30%$ ✓. Forecast check: ARR hundreds mein hai, CCR ~ek-third hai — matches.

Example 2 — Cell B: pulse-width design (servo)

Worked example ESC arming pulse: 50 Hz frame, 1.0 ms pulse

Forecast: yahan duty hai $1 ms /20 ms = 5%$ — lekin kya hum kabhi kahin 5% type karte hain? (Nahi — dekhte hain kyun.)

Given: $f_{c l k} = 72 MHz$ , frame rate $50 Hz$ (period $20 ms$ ), pulse width $1.0 ms$ .

Phir se tidy tick. $P S C = 71 \Rightarrow f_{t im} = 1 MHz \Rightarrow t_{t i c k} = 1 μ s$ . Kyun? ESC/servo ko pulse ki duration microseconds mein chahiye; 1 µs ticks se hum wo duration literally µs count karke set kar sakte hain.
Frame period se ARR. $20 ms = 20000 μ s \Rightarrow A R R + 1 = 20000 \Rightarrow A R R = 19999$ . Kyun? Ek counter wrap ek 20 ms frame ke barabar hona chahiye.
CCR = pulse in ticks. $1.0 ms = 1000 μ s \Rightarrow C C R = 1000$ . Kyun? Hum CCR ko desired width par set karte hain, na ki percentage par — servo/ESC width decode karta hai, isliye µs natural unit hai.

Verify: width $= 1000 \times 1 μ s = 1 ms$ ✓. Frame $= 20000 \times 1 μ s = 20 ms = 50 Hz$ ✓. Duty nikalta hai $1000/20000 = 5%$ ✓ — sahi hai lekin kabhi type nahi kiya.

Example 3 — Cell C: degenerate duties (0%, 100%)

Worked example ARR = 999 ke saath full-off aur full-on

Forecast: truly solid-HIGH pin paane ke liye, kya $C C R = 999$ kaafi hai, ya $1000$ hona chahiye?

Given: $A R R = 999$ ⇒ total ticks per cycle $= A R R + 1 = 1000$ .

0% (pin always LOW). $C C R = 0$ set karo. Rule "HIGH while $C N T < C C R$ " kabhi true nahi hoti kyunki $C N T$ $0$ se start karta hai aur $0 < 0$ false hai. Ye step kyun? Ye dikhata hai ki boundary ek strict less-than hai, isliye $C C R = 0$ HIGH-time ko zero kar deta hai.
Near-100%. $C C R = 999$ set karo. HIGH while $C N T < 999$ , yaani counts $0..998$ = $999$ ticks. Duty $= 999/1000 = 99.9%$ — $C N T = 999$ par ek-tick LOW glitch rehti hai. Kyun? Ye classic off-by-one demonstrate karta hai: $A R R$ full-on value NAHI hai.
True 100%. $C C R = 1000 = A R R + 1$ set karo. Ab $C N T < 1000$ sab counts $0..999$ ke liye ⇒ har tick par HIGH. Duty $= 1000/1000 = 100%$ . Kyun? Sirf $C C R = A R R + 1$ hi compare ko poore cycle ke liye hold karwata hai.

Verify: duties hain $0/1000 = 0%$ , $999/1000 = 99.9%$ , $1000/1000 = 100%$ ✓. Ye bilkul wahi [!mistake] "duty is CCR/ARR" trap hai parent se — $A R R = 999$ ko "100%" value use karne par $999/1000$ milta hai, jo galat hai.

Example 4 — Cell D: toggle mode square wave

Worked example Toggle-on-match se exact 250 kHz square wave

Forecast: toggle mode mein har match pin flip karta hai. Toh 250 kHz wave produce karne ke liye, timer ko 250 kHz par match karna chahiye ya 500 kHz par?

Given: $f_{c l k} = 72 MHz$ , $P S C = 0 \Rightarrow f_{t im} = 72 MHz$ , target $f_{o u t} = 250 kHz$ .

Toggles per period count karo. Ek full square wave = ek HIGH half + ek LOW half = do flips. Ye step kyun? Output frequency match rate ki half hoti hai, isliye ARR choose karne se pehle target ko double karna hoga.
Required match rate. $f_{ma t c h} = 2 f_{o u t} = 500 kHz$ . Kyun? Har match ek toggle hai; 250k full cycles/s banane ke liye 500k toggles/s chahiye.
ARR solve karo. Matches har wrap par hote hain: $f_{ma t c h} = f_{t im} / (A R R + 1) \Rightarrow A R R + 1 = 72 M /500 k = 144 \Rightarrow A R R = 143$ . Kyun? Same period formula, lekin yahan "period" toggles ke beech ka interval hai, na ki full waves ke beech ka.

Verify: toggle interval $= 144/72 MHz = 2 μ s$ ; unme se do $= 4 μ s$ ⇒ $f_{o u t} = 1/4 μ s = 250 kHz$ ✓.

Example 5 — Cell E: input capture, no overflow

Worked example Ek unknown clean signal measure karo

Forecast: do rising-edge captures $c_{1} = 1500$ , $c_{2} = 4000$ at 1 µs/tick. Kya gap 2.5 ms hai ya 2500 µs? (Trick: dono same hain!)

Given: $f_{t im} = 1 MHz$ ( $t_{t i c k} = 1 μ s$ ), $A R R = 65535$ , $c_{1} = 1500$ , $c_{2} = 4000$ . No wrap (kyunki $c_{2} > c_{1}$ aur counter bada hai).

Elapsed ticks. $Δ = c_{2} - c_{1} = 4000 - 1500 = 2500$ . Ye step kyun? Input capture CNT ko har edge par snapshot karta hai; difference hi elapsed count hai — koi software delay nahi.
Time mein convert karo. $T_{s i g na l} = Δ t_{t i c k} = 2500 \times 1 μ s = 2500 μ s = 2.5 ms$ . Kyun? Har tick ek known 1 µs hai, isliye ticks seedha microseconds se map hote hain.
Frequency ke liye invert karo. $f_{s i g na l} = 1/ T_{s i g na l} = 1/2.5 ms = 400 Hz$ . Kyun? Frequency us period ka reciprocal hai jo humne abhi measure ki.

Verify: $1/ (2500 \times 1 0^{- 6} s) = 400 Hz$ ✓, aur $Δ = 2500 < 65536$ confirm karta hai no wrap ✓.

Example 6 — Cell F: input capture ACROSS an overflow

Worked example Negative-difference trap

Forecast: $c_{1} = 64000$ , $c_{2} = 1500$ , $A R R = 65535$ . Raw subtraction deta hai $- 62500$ . Kya real gap isliye negative time (impossible) hai, ya counter ek baar wrap hua?

Given: $f_{t im} = 1 MHz$ , $A R R = 65535$ ⇒ modulus $= A R R + 1 = 65536$ , $c_{1} = 64000$ , $c_{2} = 1500$ .

Wrap spot karo. $c_{2} < c_{1}$ bhi hai jabki time aage gaya ⇒ counter edges ke beech overflow hua. Ye step kyun? Ek forward time gap kabhi smaller count nahi de sakta jab tak counter beech mein 0 par reset na ho.
Modulo apply karo. $Δ = (c_{2} - c_{1}) mod (A R R + 1) = (1500 - 64000) mod 65536 = 65536 - 62500 = 3036$ . Kyun? Ek pura modulus $65536$ add karne se single wrap "undo" hoti hai, aur true forward count restore hota hai.
Convert karo. $T_{s i g na l} = 3036 \times 1 μ s = 3036 μ s \Rightarrow f_{s i g na l} = 1/3036 μ s \approx 329.4 Hz$ . Kyun? Same tick→time→frequency chain jaisi Example 5 mein, ab corrected $Δ$ par.

Verify: $65536 - 62500 = 3036$ ✓; $1/ (3036 \times 1 0^{- 6}) \approx 329.38 Hz$ ✓. Mod ignore karne se negative period ke saath math crash ho jata.

Example 7 — Cell G: 16-bit timer ki limiting frequencies

Worked example 72 MHz par 16-bit ARR ke saath slowest aur fastest PWM

Forecast: $P S C = 0$ ke saath, highest PWM frequency guess karo (sabse chhote usable ARR se limited) aur lowest (max ARR = 65535 se limited).

Given: $f_{c l k} = 72 MHz$ , 16-bit timer ⇒ $A R R \in [1, 65535]$ (wave banane ke liye $\geq 2$ ticks chahiye), extreme high end ke liye $P S C = 0$ .

Fastest PWM. Sabse chhoti wave $A R R = 1$ use karti hai ⇒ $A R R + 1 = 2$ ⇒ $f_{P W M} = 72 M /2 = 36 MHz$ . Ye step kyun? Fewer ticks per cycle = higher frequency; $A R R = 1$ (2 ticks) sabse coarse lekin fastest square wave hai, lekin duty resolution sirf 0%/50%/100% hai.
Lowest PWM (PSC=0 abhi bhi). Largest $A R R = 65535$ ⇒ $A R R + 1 = 65536$ ⇒ $f_{P W M} = 72 M /65536 \approx 1098.6 Hz$ . Kyun? Max ARR period ko utna stretch karta hai jitna ek 16-bit counter PSC badhane se pehle allow karta hai.
PSC se aur slow jao. ~1 Hz reach karne ke liye $(P S C + 1) (A R R + 1) = 72 M$ chahiye. $A R R = 65535$ ke saath: $P S C + 1 = 72 M /65536 \approx 1098.6 \Rightarrow P S C = 1098$ deta hai $f \approx 1.0006 Hz$ . Kyun? Do dividers multiply karte hain, isliye PSC wo range extend karta hai jo 16-bit ARR akela nahi kar sakta.

Verify: $72 M /2 = 36 MHz$ ✓; $72 M /65536 \approx 1098.63 Hz$ ✓; $72 M / ((1098 + 1) \cdot 65536) \approx 1.0006 Hz$ ✓.

Example 8 — Cell H: real-world word problem (LED dimming)

Worked example "Is status LED ko 20% bright dikhao, flicker-free."

Forecast: aankhein ~100 Hz se upar flicker fuse karti hain. Kya hum 20 Hz, 200 Hz, ya 20 kHz ka PWM frequency choose karein? Aur kya "20% bright" seedha duty mein translate hota hai?

Given: $f_{c l k} = 8 MHz$ (ek chhota MCU), koi visible flicker nahi chahiye, perceived brightness ≈ 20%.

Flicker-free frequency choose karo. $f_{P W M} = 1 kHz$ pick karo (~100 Hz fusion limit se kaafi upar, aankhon ke liye easy). Ye step kyun? ~100 Hz se neeche LED visible blink karta hai; 1 kHz smooth dimming guarantee karta hai.
Tidy tick + ARR. $P S C = 7 \Rightarrow f_{t im} = 8 M /8 = 1 MHz$ (1 µs). $A R R + 1 = 1 M /1 k = 1000 \Rightarrow A R R = 999$ . Kyun? 1 MHz trick reuse karo, phir ARR ke liye period formula invert karo.
20% ke liye duty. Coarse brightness ke liye hum treat karte hain perceived ≈ duty: $C C R = 0.20 \times 1000 = 200$ . Kyun? Average LED current ∝ duty, isliye 20% duty roughly 20% average current deta hai (real aankhein gamma-nonlinear hain, lekin ye standard first-order mapping hai).

Verify: $f = 1 M /1000 = 1 kHz$ (flicker-free) ✓; duty $= 200/1000 = 20%$ ✓.

Example 9 — Cell I: exam twist (scope se reverse-engineer)

Worked example Scope 4 kHz signal dikhata hai jo 75 µs HIGH hai. ARR aur CCR find karo.

Forecast: unhone tumhe screen par time diya hai, registers nahi. Kaun sa formula pehle invert karte ho — period ya duty?

Given: $f_{c l k} = 64 MHz$ , observed $f_{P W M} = 4 kHz$ , observed HIGH time $= 75 μ s$ . Tum PSC choose karo.

Tick pick karo, ARR find karo. $P S C = 63 \Rightarrow f_{t im} = 64 M /64 = 1 MHz$ (1 µs). Period $= 1/4 kHz = 250 μ s \Rightarrow A R R + 1 = 250 \Rightarrow A R R = 249$ . Ye step kyun? $f_{P W M} = f_{t im} / (A R R + 1)$ invert karo; observed period total tick count deta hai.
HIGH time → CCR directly. HIGH $75 μ s = 75$ ticks tak rehti hai ⇒ $C C R = 75$ . Kyun? 1 µs ticks ke saath, HIGH-microseconds = HIGH-ticks = CCR.
Duty cross-check karo. $D = C C R / (A R R + 1) = 75/250 = 30%$ , aur wakai $75 μ s /250 μ s = 30%$ . Kyun? Same duty ke do independent routes confirm karte hain ki registers consistent hain.

Verify: $f_{t im} / (A R R + 1) = 1 M /250 = 4 kHz$ ✓; HIGH $= 75 \times 1 μ s = 75 μ s$ ✓; duty $= 75/250 = 30%$ ✓.

Parent topic (Hinglish) — wo machinery jin par ye examples exercise karte hain.
Clock Tree and Prescalers — jahan se $f_{c l k}$ aur tidy-tick choices aate hain.
GPIO and Alternate Functions — wo pin jo har PWM/toggle example drive karta hai.
Interrupts and NVIC — Cell F wrap case ke liye overflow-counting.
Servo and ESC Control — Example 2 ki pulse-width interpretation.
Motor Control and H-Bridges — Example 1 & 8 style duty control at speed.
Encoder Mode — curious logon ke liye ek capture cousin.

Worked examples — Timers — PWM generation, input capture, output compare