Exercises — Timers — PWM generation, input capture, output compare

The divider is $(PSC+1)$, not PSC. To divide by 8: $PSC+1=8\Rightarrow PSC=7$.

• Output Compare / PWM: Timer → Pin (the count reaches CCR, hardware drives the pin).
• Input Capture: Pin → Timer (an edge on the pin copies CNT into CCR). Mnemonic: Compare = Control the pin; Capture = Copy the time.

ARR sets the period (the whole saw-tooth length). CCR sets the HIGH duration (how far up the plum line sits). Frequency stays fixed as you change duty — only the orange split moves.

(a) $f_{tim}=\frac{72\text{MHz}}{71+1}=\frac{72\times 10^6}{72}=1\text{MHz}$ → each tick is $1\mu s$. (b) The counter sweeps $0\to 999$, i.e. $ARR+1=1000$ ticks per period, so $f_{PWM}=\frac{f_{tim}}{ARR+1}=\frac{10^6}{1000}=1000\text{Hz}=1\text{kHz}$. (c) $D=\frac{CCR}{ARR+1}\times 100\%=\frac{250}{1000}\times 100\%=25\%$.

Keep $1\mu s$ ticks ⇒ $f_{tim}=1\text{MHz}$ ⇒ $PSC=71$. Period $T=\frac{1}{2000\text{Hz}}=500\mu s=500$ ticks. Because the sweep takes $(ARR+1)$ ticks, $ARR+1=500\Rightarrow \boxed{ARR=499}$. Duty: $CCR=0.75\times (ARR+1)=0.75\times 500=\boxed{375}$.

$1\mu s$ ticks ⇒ $PSC=71$. Frame $T=20\text{ms}=20000$ ticks $=(ARR+1)$ ⇒ $ARR=19999$. Servos read the pulse width directly, so $CCR=2.0\text{ms}=2000$ ticks. → CCR=2000. (See Servo and ESC Control for why width, not duty %, is what the servo decodes.)

The scope is right; the student divided by the wrong number. Duty is $\frac{CCR}{ARR+1}=\frac{500}{1000}=50.0\%$, not $CCR/ARR$. The counter has $ARR+1=1000$ distinct tick-slots per period (it spends one tick at each of $0\dots 999$), and HIGH occupies CCR=500 of them → exactly half. Using $ARR$ (=999) in the denominator invents a phantom $0.05\%$ error that the hardware never had.

The counter wrapped once between the two edges (it hit 65535, reset to 0, then kept counting). Raw subtraction goes negative because it ignores the wrap. Here $\mathrm{mod}(ARR+1)$ means "the non-negative remainder after removing whole counter cycles of length $(ARR+1)=65536$" — it adds back one full cycle to a negative difference. So: $\Delta =(c_2-c_1)\mathrm{mod}65536=(1500-60000)\mathrm{mod}65536=-58500+65536=7036\text{ ticks}.$ At $1\mu s$/tick: $T=7036\mu s\approx 7.036\text{ms}$, so $f_{signal}=\frac{1}{7.036\text{ms}}\approx 142.1\text{Hz}$.

$f_{tim}=72$ MHz, so overflows occur every $ARR+1=100$ ticks → overflow rate $=72\times 10^6/100=720$ kHz. But toggle flips the pin each overflow, and it takes two flips (HIGH→LOW→HIGH) for one full wave. So $f_{out}=720\text{kHz}/2=360\text{kHz}$.

Use $1\mu s$ ticks → $PSC=71$, $f_{tim}=1$ MHz. Frame $T=\frac{1}{400\text{Hz}}=2.5\text{ms}=2500$ ticks $=(ARR+1)$ ⇒ $ARR=2499$. Idle pulse $1.0\text{ms}=1000$ ticks ⇒ $CC{R}_{idle}=1000$. Full pulse $2.0\text{ms}=2000$ ticks ⇒ $CC{R}_{full}=2000$. Fits? Longest pulse (2000) is well under the frame (2500) → yes, comfortable margin. (See Servo and ESC Control.)

With $PSC=71$ ($f_{tim}=1$ MHz), a 1 Hz period needs $ARR+1=10^6$ ⇒ $ARR=999999$ — far above the 16-bit ceiling of 65535. Impossible. How to choose the divisor: the total division is $(PSC+1)(ARR+1)=f_{clk}/f_{PWM}=72\times 10^6$. We must split this product into two factors that each fit in 16 bits ($\le 65536$). A tidy split is to make $f_{tim}$ a round number: pick $PSC=7199$ ⇒ $f_{tim}=\frac{72\times 10^6}{7200}=10\text{kHz}$ (tick $=100\mu s$), leaving $ARR+1=10000$ ($ARR=9999$) — both comfortably under 65536. (Many splits work; this one keeps the tick a clean $100\mu s$.) Period 1 Hz $=1\text{s}=10000$ ticks ⇒ $ARR=9999$ (fits!). Duty 10 %: $CCR=0.10\times 10000=1000$. Check: $f_{PWM}=\frac{72\times 10^6}{7200\times 10000}=\frac{72\times 10^6}{7.2\times 10^7}=1\text{Hz}$. ✓

HIGH holds while $CNT<CCR$, across $CNT=0\dots 999$ ($ARR+1=1000$ slots).

• 0 %: $CCR=0$ → the condition $CNT<0$ is never true → pin never HIGH.
• 100 %: need HIGH for all 1000 slots → $CCR=ARR+1=1000$. Wait — can CCR exceed ARR? Yes. The compare register is not clamped to ARR; it is just a 16-bit value the hardware compares against. If $CCR>ARR$, the counter never reaches or exceeds CCR during its $0\dots ARR$ sweep, so the "go LOW" condition never fires and the pin stays HIGH for the whole cycle — exactly the 100 % we want. Then $CNT<1000$ is true for every count $0\dots 999$.
• $CCR=999$ leaves the single slot $CNT=999$ LOW → duty $=999/1000=99.9\%$, not 100 %. The missing tick is the classic "almost-but-not-quite full brightness" bug.

Let $k$ = number of full counter overflows between the two edges; here $k=3$. Each full cycle is $ARR+1=65536$ ticks, so the true gap adds $k$ whole cycles onto the raw difference: $\Delta =k(ARR+1)+(c_2-c_1)=3\times 65536+(10000-40000)=196608-30000=166608\text{ ticks}.$ At $1\mu s$/tick: $T=166608\mu s\approx 166.6\text{ms}$, so $f_{signal}=\frac{1}{0.166608\text{s}}\approx 6.002\text{Hz}$. Single-wrap modulo would have under-counted by $2\times 65536$ ticks — you must track the overflow count $k$ for multi-cycle gaps.

The counter wrapped once. Recall $\mathrm{mod}65536$ means "add back one full cycle to a negative difference": $\Delta =(c_f-c_r)\mathrm{mod}65536=(200-64000)\mathrm{mod}65536=-63800+65536=1736\text{ ticks}.$ At $1\mu s$/tick the HIGH pulse is $1736\mu s=1.736\text{ms}$. (This is exactly how H-bridge current-sense timing gets measured.)

Resolution = one tick $=\frac{1}{72\text{MHz}}\approx 13.9\text{ns}$. Longest single-cycle span = $ARR+1=65536$ ticks $=\frac{65536}{72\times 10^6}\approx 910\mu s\approx 0.91\text{ms}$. Anything longer wraps and demands overflow bookkeeping — the trade-off is fine resolution vs short unambiguous range.