Exercises — Timers — PWM generation, input capture, output compare

Divider $(PSC+1)$ hai, na ki PSC. 8 se divide karne ke liye: $PSC+1=8\Rightarrow PSC=7$.

• Output Compare / PWM: Timer → Pin (count CCR tak pahunchta hai, hardware pin drive karta hai).
• Input Capture: Pin → Timer (pin par edge aati hai aur CNT ko CCR mein copy karti hai). Mnemonic: Compare = Control the pin; Capture = Copy the time.

ARR period set karta hai (poori saw-tooth length). CCR HIGH duration set karta hai (plum line kitni upar baithi hai). Frequency fixed rehti hai jab tum duty change karte ho — sirf orange split move hoti hai.

(a) $f_{tim}=\frac{72\text{MHz}}{71+1}=\frac{72\times 10^6}{72}=1\text{MHz}$ → har tick $1\mu s$ ka hai. (b) Counter $0\to 999$ sweep karta hai, yaani $ARR+1=1000$ ticks per period, toh $f_{PWM}=\frac{f_{tim}}{ARR+1}=\frac{10^6}{1000}=1000\text{Hz}=1\text{kHz}$. (c) $D=\frac{CCR}{ARR+1}\times 100\%=\frac{250}{1000}\times 100\%=25\%$.

$1\mu s$ ticks rakho ⇒ $f_{tim}=1\text{MHz}$ ⇒ $PSC=71$. Period $T=\frac{1}{2000\text{Hz}}=500\mu s=500$ ticks. Kyunki sweep $(ARR+1)$ ticks leta hai, $ARR+1=500\Rightarrow \boxed{ARR=499}$. Duty: $CCR=0.75\times (ARR+1)=0.75\times 500=\boxed{375}$.

$1\mu s$ ticks ⇒ $PSC=71$. Frame $T=20\text{ms}=20000$ ticks $=(ARR+1)$ ⇒ $ARR=19999$. Servos pulse width directly read karte hain, toh $CCR=2.0\text{ms}=2000$ ticks. → CCR=2000. (Dekho Servo and ESC Control kyun width, duty % nahi, woh hai jo servo decode karta hai.)

Scope sahi hai; student ne galat number se divide kiya. Duty hai $\frac{CCR}{ARR+1}=\frac{500}{1000}=50.0\%$, $CCR/ARR$ nahi. Counter ke paas per period $ARR+1=1000$ distinct tick-slots hain (woh $0\dots 999$ mein se har ek par ek tick spend karta hai), aur HIGH CCR=500 slots occupy karta hai → exactly half. $ARR$ (=999) ko denominator mein use karna ek phantom $0.05\%$ error invent karta hai jo hardware mein kabhi tha hi nahi.

Counter dono edges ke beech ek baar wrap hua (woh 65535 hit kiya, 0 par reset hua, phir count karta raha). Raw subtraction negative jaati hai kyunki yeh wrap ignore karti hai. Yahan $\mathrm{mod}(ARR+1)$ ka matlab hai "$(ARR+1)=65536$ length ke poore counter cycles hatane ke baad non-negative remainder" — yeh ek negative difference mein ek full cycle wapas jodhta hai. Toh: $\Delta =(c_2-c_1)\mathrm{mod}65536=(1500-60000)\mathrm{mod}65536=-58500+65536=7036\text{ ticks}.$ $1\mu s$/tick par: $T=7036\mu s\approx 7.036\text{ms}$, toh $f_{signal}=\frac{1}{7.036\text{ms}}\approx 142.1\text{Hz}$.

$f_{tim}=72$ MHz, toh overflows har $ARR+1=100$ ticks par hote hain → overflow rate $=72\times 10^6/100=720$ kHz. Lekin toggle har overflow par pin flip karta hai, aur ek poori wave ke liye do flips chahiye (HIGH→LOW→HIGH). Toh $f_{out}=720\text{kHz}/2=360\text{kHz}$.

$1\mu s$ ticks use karo → $PSC=71$, $f_{tim}=1$ MHz. Frame $T=\frac{1}{400\text{Hz}}=2.5\text{ms}=2500$ ticks $=(ARR+1)$ ⇒ $ARR=2499$. Idle pulse $1.0\text{ms}=1000$ ticks ⇒ $CC{R}_{idle}=1000$. Full pulse $2.0\text{ms}=2000$ ticks ⇒ $CC{R}_{full}=2000$. Fit hoti hai? Longest pulse (2000) frame (2500) se kaafi kam hai → haan, comfortable margin. (Dekho Servo and ESC Control.)

$PSC=71$ ke saath ($f_{tim}=1$ MHz), 1 Hz period ke liye $ARR+1=10^6$ chahiye ⇒ $ARR=999999$ — 16-bit ceiling 65535 se bahut upar. Impossible. Divisor choose kaise karein: total division hai $(PSC+1)(ARR+1)=f_{clk}/f_{PWM}=72\times 10^6$. Humein is product ko do factors mein split karna hai jo dono 16 bits mein fit hon ($\le 65536$). Ek clean split $f_{tim}$ ko round number banana hai: $PSC=7199$ lo ⇒ $f_{tim}=\frac{72\times 10^6}{7200}=10\text{kHz}$ (tick $=100\mu s$), chhod ke $ARR+1=10000$ ($ARR=9999$) — dono comfortably 65536 se neeche. (Kai splits kaam karenge; yeh wala tick ko ek clean $100\mu s$ rakhta hai.) Period 1 Hz $=1\text{s}=10000$ ticks ⇒ $ARR=9999$ (fits!). Duty 10 %: $CCR=0.10\times 10000=1000$. Check: $f_{PWM}=\frac{72\times 10^6}{7200\times 10000}=\frac{72\times 10^6}{7.2\times 10^7}=1\text{Hz}$. ✓

HIGH hold karta hai jab $CNT<CCR$, $CNT=0\dots 999$ ($ARR+1=1000$ slots) across.

• 0 %: $CCR=0$ → condition $CNT<0$ kabhi true nahi → pin kabhi HIGH nahi.
• 100 %: saare 1000 slots ke liye HIGH chahiye → $CCR=ARR+1=1000$. Ruko — kya CCR ARR se zyada ho sakta hai? Haan. Compare register ARR tak clamped nahi hai; yeh sirf ek 16-bit value hai jise hardware compare karta hai. Agar $CCR>ARR$, counter kabhi $0\dots ARR$ sweep ke dauran CCR tak nahi pahunchta ya cross nahi karta, toh "go LOW" condition kabhi fire nahi hoti aur pin poore cycle ke liye HIGH rehta hai — exactly woh 100 % jo hum chahte hain. Tab $CNT<1000$ har count $0\dots 999$ ke liye true hai.
• $CCR=999$ single slot $CNT=999$ LOW chhod deta hai → duty $=999/1000=99.9\%$, 100 % nahi. Missing tick classic "almost-but-not-quite full brightness" bug hai.

Maano $k$ = dono edges ke beech poore counter overflows ki sankhya; yahan $k=3$. Har full cycle $ARR+1=65536$ ticks ki hai, toh true gap raw difference mein $k$ poore cycles jodhta hai: $\Delta =k(ARR+1)+(c_2-c_1)=3\times 65536+(10000-40000)=196608-30000=166608\text{ ticks}.$ $1\mu s$/tick par: $T=166608\mu s\approx 166.6\text{ms}$, toh $f_{signal}=\frac{1}{0.166608\text{s}}\approx 6.002\text{Hz}$. Single-wrap modulo $2\times 65536$ ticks under-count karta — multi-cycle gaps ke liye tumhe overflow count $k$ zaroor track karna chahiye.

Counter ek baar wrap hua. Yaad karo $\mathrm{mod}65536$ ka matlab hai "ek negative difference mein ek full cycle wapas jodho": $\Delta =(c_f-c_r)\mathrm{mod}65536=(200-64000)\mathrm{mod}65536=-63800+65536=1736\text{ ticks}.$ $1\mu s$/tick par HIGH pulse $1736\mu s=1.736\text{ms}$ hai. (Bilkul aise hi H-bridge current-sense timing measure hoti hai.)

Resolution = ek tick $=\frac{1}{72\text{MHz}}\approx 13.9\text{ns}$. Longest single-cycle span = $ARR+1=65536$ ticks $=\frac{65536}{72\times 10^6}\approx 910\mu s\approx 0.91\text{ms}$. Isse longer kuch bhi wrap karta hai aur overflow bookkeeping demand karta hai — trade-off hai fine resolution vs short unambiguous range.