Microcontroller architecture — ARM Cortex-M series (M0, M3, M4, M7): Worked examples

5.5.1 · D3 · Coding › Embedded Systems & Real-Time Software › Microcontroller architecture — ARM Cortex-M series (M0, M3,

Yeh page parent note ke ideas ke liye ek bada practice arena hai. Yahan hum koi naya theory nahi seekhenge — balki parent ne jo teen formulas banaye hain (pipeline cycles, superscalar IPC, interrupt latency), unhe har us corner case mein push karenge jo ek real embedded engineer ko milti hai: chhoti inputs, badi inputs, "trap" answer, degenerate answer, word problem, aur exam twist.

Kisi bhi example se pehle, teen tools ko plain words mein re-state karte hain taaki kuch bhi unexplained na lage.

Recall Teen formulas jo hum baar baar use karenge (parent se)

1. Pipeline cycles. Ek $N$ -stage pipeline ek assembly line hai jisme $N$ work-stations hain. Pehla instruction saare $N$ stations se guzarne ke baad hi finish hota hai; uske baad har instruction ek clock baad finish hoti hai. To $I$ instructions ke liye: $Cycles = (N - 1) + I$ $(N - 1)$ ek baar ka "pipe fill karo" tax hai.

2. Superscalar IPC. IPC = Instructions Per Cycle. Ek normal core har cycle mein 1 finish karta hai ( $IPC = 1$ ). Ek dual-issue core (jaise M7) ek saath 2 start kar sakta hai, lekin sirf tab jab instructions ka ek pair itna independent ho. Agar $p$ fraction pairs saath chal sakti hain, aur machine $w$ -wide hai: $IPC = 1 + p (w - 1)$

3. Interrupt latency. Jab interrupt fire hota hai, CPU ko (a) use notice karna hota hai, (b) 8 registers stack karne hote hain, aur (c) wait karna hota hai agar koi zyada urgent cheez already chal rahi ho: $L_{m a x} = t_{detect} + t_{stack} + t_{higher-prio busy}$

Upar har symbol ( $N$ , $I$ , $w$ , $p$ , $L_{m a x}$ ) ab define ho gaya hai. Acha — ab cases ka map banate hain.

The scenario matrix

Is topic ke har problem ko ek cell mein girta hua socho. Agar hum ek cell mein ek example solve karein, toh reader ko koi unseen scenario nahi milega.

#	Case class	Kya tricky banata hai	Example jo hit karta hai
A	Single pass, chhota $I$	Fill tax dominate karta hai	Ex 1
B	Bahut saare passes, bada $I$	Fill tax negligible ho jaata hai	Ex 2
C	Degenerate: $I = 0$ ya $I = 1$	Formula phir bhi sense banana chahiye	Ex 3
D	Limiting: $I \to \infty$	Average cycles/instr $\to 1$	Ex 3
E	Superscalar, $p = 0$ vs $p = 1$	Dual-issue ke do extremes	Ex 4
F	Superscalar realistic $p$	Fractional, real-world value	Ex 4
G	Interrupt latency, no blocking	Best case ( $t_{busy} = 0$ )	Ex 5
H	Interrupt latency, nested/blocked	Worst case, higher-prio chal raha hai	Ex 5
I	Word problem (deadline)	Cycles ↔ time convert karo clock ke zariye	Ex 6
J	Exam twist: `double` trap	Hidden software emulation	Ex 7
K	Exam twist: deep-pipe misprediction	"Zyada stages" ulta pad jaata hai	Ex 8

Neeche har figure ek derivation ki geometry carry karta hai — sirf numbers nahi, arrows bhi dekho.

Worked examples

Ex 1 — Cell A: ek pass, fill tax kaata hai

Worked example Ek 6-instruction loop ka ek pass on M0 (2-stage pipeline)

Ek loop body mein $I = 6$ instructions hain. M0 mein $N = 2$ stages hain. Ek pass ke liye kitne cycles chahiye?

Forecast: padhne se pehle andaaza lagao — kya yeh 6, 7, ya 8 cycles hoga?

Formula likho: $Cycles = (N - 1) + I$ . Yeh step kyun? Yeh tool 1 hai; pipe ek baar fill hoti hai, phir stream karta hai.
$N = 2, I = 6$ substitute karo: $Cycles = (2 - 1) + 6 = 1 + 6 = 7$ . Yeh step kyun? $(N - 1) = 1$ woh single "warm-up" cycle hai jo pehli instruction pay karti hai; neeche assembly-line figure dekho — pehle block ko exit karne ke liye 2 stations chahiye, isliye steady stream se pehle exactly 1 extra cycle aata hai.

Answer: 7 cycles.

Verify: Haath se trace karo. Cycle 1: instr-1 stage F mein. Cycle 2: instr-1 stage E mein (finish!), instr-2 stage F mein. Cycle 2 se aage har cycle mein ek instruction finish hoti hai. Instr-1 cycle 2 par finish hoti hai, instr-6 cycle 2+5 = 7 par finish hoti hai. ✓ Match karta hai.

Ex 2 — Cell B: bahut saare passes, tax fade ho jaata hai

Worked example Usi 6-instruction loop ke 1000 passes

Wohi M0, wohi body ( $I = 6$ per pass, $N = 2$ ). Ab 1000 passes chalao. Naive guess: $1000 \times 7 = 7000$ ?

Forecast: kya yeh exactly $7000$ hoga, ya kam?

Saare passes mein total instructions: $I_{tot} = 1000 \times 6 = 6000$ . Yeh step kyun? Pipe iterations ke beech mein drain nahi hoti — instructions flow karte rehte hain — isliye hum saare passes ko ek lamba stream maante hain.
Tool 1 ek baar apply karo: $Cycles = (N - 1) + I_{tot} = 1 + 6000 = 6001$ . Yeh step kyun? Fill tax ek baar pay karte ho, bilkul shuru mein, har loop par nahi. Isliye answer naive $7000$ se behtar hai.

Answer: 6001 cycles, 7000 nahi.

Verify: Naive se difference $= 7000 - 6001 = 999$ . Yeh exactly $999$ saved fill-cycles hain — pehle pass ke baad har pass mein ek bachata hai (pehla pass apna tax rakhta hai). $999 = 1000 - 1$ . ✓ Sanity theek hai.

Ex 3 — Cells C & D: degenerate aur limiting inputs

Worked example Formula edges par kya karta hai?

M3 par ( $N = 3$ ), evaluate karo: (a) $I = 0$ instructions, (b) $I = 1$ instruction, (c) average cycles-per-instruction jab $I \to \infty$ .

Forecast: kya $I = 0$ se $0$ cycles milte hain ya kuch ajeeb?

(a) $I = 0$ : $Cycles = (3 - 1) + 0 = 2$ . Yeh step kyun? Koi useful kaam nahi hota, phir bhi agar aapne pipe fill karna shuru kiya toh 2 warm-up cycles spend ho gayi. Practice mein zero instructions wala real program kuch nahi chalata, isliye honest reading yeh hai: formula woh fill cost describe karta hai jo aap debt mein hote — $I = 0$ ko "sirf tax" socho. Saaf, physical value 2 cycles of pure overhead hai.
(b) $I = 1$ : $Cycles = (3 - 1) + 1 = 3$ . Yeh step kyun? Ek akela instruction finish hone ke liye saare $N = 3$ stations traverse karna hoga — isliye exactly $N = 3$ cycles lagte hain. Formula $3$ deta hai. ✓ "Ek instruction = full pipe depth" se consistent.
(c) Limit: average cycles/instr $= \frac{( N - 1 ) + I}{I} = 1 + \frac{N - 1}{I}$ . Jab $I \to \infty$ , doosra term $\to 0$ , toh average $\to 1$ . Yeh step kyun? Isliye pipelining worth it hai: long streams par har instruction essentially ek cycle karti hai, yaani $IPC_{ideal} = 1$ .

Answers: (a) $2$ , (b) $3$ , (c) $\to 1$ .

Verify: $I = 3, N = 3$ average mein plug karo: $1 + 2/3 \approx 1.667$ ; aur directly $(3 - 1) + 3 = 5$ cycles for $3$ instr $= 5/3 \approx 1.667$ . ✓ Dono routes agree karte hain, toh limit reasoning sound hai.

Ex 4 — Cells E & F: dual-issue ke do extremes aur middle

Worked example M7 superscalar IPC at

$p = 0$ , $p = 1$ , aur realistic $p = 0.4$ M7 dual-issue hai, toh $w = 2$ . Teen code styles ke liye IPC compute karo: fully serial ( $p = 0$ ), perfectly parallel pairs ( $p = 1$ ), aur typical C code ( $p = 0.4$ ).

Forecast: $w = 2$ core ki maximum IPC kabhi bhi kitni ho sakti hai?

Formula (tool 2): $IPC = 1 + p (w - 1)$ . $w = 2$ ke saath: $IPC = 1 + p$ . Yeh step kyun? $(w - 1) = 1$ formula ko collapse kar deta hai toh IPC bas "1 plus fraction of pairs that fused" hai.
$p = 0$ : $IPC = 1 + 0 = 1$ . Kyun? Koi bhi pair kabhi saath issue nahi hoti → doosra pipe lane idle hai → effectively single-issue ho gaye. Yeh lower bound hai.
$p = 1$ : $IPC = 1 + 1 = 2$ . Kyun? Har cycle mein do instructions fuse hoti hain → har cycle mein 2 finish. Yeh $w = 2$ ke liye hard ceiling hai — machine width se kabhi zyada nahi ja sakte.
$p = 0.4$ : $IPC = 1 + 0.4 = 1.4$ . Kyun? Real code mein dependencies hoti hain (ek instruction ko pichla result chahiye), isliye sirf ~40% pairs fuse hoti hain. Figure dekho — teal pairs fuse hoti hain, orange singletons nahi.

Answers: $1$ , $2$ , $1.4$ .

Verify: IPC ko $1 \leq IPC \leq w = 2$ satisfy karna chahiye kisi bhi valid $p \in [0, 1]$ ke liye. Teeno ( $1, 1.4, 2$ ) $[1, 2]$ mein hain. ✓ Aur $p = 0.4$ ki value $1.4$ single-issue par $1.4 \times$ speedup imply karti hai — parent ke "IPC ≈ 1.3–1.5" claim se match karta hai.

Ex 5 — Cells G & H: interrupt latency, best aur worst

Worked example M4 par interrupt ki latency, busy higher-priority handler ke saath aur bina

Assume karo $t_{detect} = 1$ cycle (sync), $t_{stack} = 12$ cycles (automatic 8-register push). Compute karo (G) best case jab kuch block nahi kar raha, aur (H) worst case jab ek higher-priority IRQ mid-execution hai aur return karne se pehle $40$ aur cycles chalega.

Forecast: ek blocking handler latency ko kitna inflate karta hai?

(G) Best case: $t_{higher-prio busy} = 0$ . $L = 1 + 12 + 0 = 13$ cycles. Yeh step kyun? Kuch zyada urgent nahi chal raha, toh NVIC stack karke seedha jump karta hai — sirf noticing (1) aur stacking (12) ka cost hai. Timeline figure dekho: green bar chhota hai.
(H) Worst case: higher-priority handler pehle finish hona chahiye, toh $t_{higher-prio busy} = 40$ . $L_{m a x} = 1 + 12 + 40 = 53$ cycles. Yeh step kyun? Aapka interrupt ready hai lekin CPU legally ek zyada important se busy hai — determinism ka matlab hai yeh term bounded aur knowable hai, zero nahi. Figure mein red segment woh 40-cycle wait hai.

Answers: best $13$ cycles, worst $53$ cycles.

Verify: Worst − best $= 53 - 13 = 40$ , exactly woh blocking term jo humne inject kiya. ✓ Formula apne teen bounded pieces mein additive hai, yahi NVIC ke deterministic design ka poora point hai.

Ex 6 — Cell I: real-world deadline word problem

Worked example Kya ek 20 kHz control loop M4 par 168 MHz par apni deadline meet karega?

Ek motor-control ISR har $50 μ s$ mein run hota hai (yeh 20 kHz hai). Uska body $I = 800$ instructions hai ek $3$ -stage pipeline par, plus ek fixed $13$ -cycle interrupt entry (Ex 5 se, best case). M4 clock $168 MHz$ hai. Kya yeh fit hoga?

Forecast: andaaza lagao ki yeh $50 μ s$ budget ka kitna fraction khaata hai — aadhe se kam, ya zyada?

Execution cycles compute karo: $(N - 1) + I = (3 - 1) + 800 = 802$ cycles. Yeh step kyun? ISR body ke liye tool 1.
Interrupt entry overhead add karo: $802 + 13 = 815$ cycles total per ISR. Yeh step kyun? Deadline ko entry + work cover karna chahiye, sirf loop nahi.
Cycles ko time mein convert karo. $168 MHz$ par ek cycle $\frac{1}{168 \times 1 0 ^{6}} s$ chalta hai. Time $= \frac{815}{168 \times 1 0 ^{6}} s = 4.851 \times 1 0^{- 6} s \approx 4.85 μ s$ . Yeh step kyun? $time = cycles \div frequency$ — frequency cycles-per-second hai, toh divide karne se cycles cancel ho jaate hain aur seconds bachte hain. Units: $\frac{cycles}{cycles/s} = s$ . ✓
$50 μ s$ budget se compare karo: $4.85 μ s < 50 μ s$ . Fit ho jaata hai kaafi room ke saath. Yeh step kyun? Real-time mein deadline matter karti hai, aur $4.85 ≪ 50$ .

Answer: Haan — yeh $50 μ s$ window mein se $\approx 4.85 μ s$ use karta hai ( $\approx 9.7%$ ).

Verify: Utilisation $= 4.85/50 = 0.097 = 9.7%$ . $100%$ se kaafi neeche, toh RTOS ke paas abhi bhi har period ka $\approx 90%$ doosre tasks ke liye free hai. ✓

Ex 7 — Cell J: `double` trap (exam twist)

Worked example M4F par do tareekon se likhe PID loop ka cycle count

M4F mein ek single-precision hardware FPU hai (dekho Fixed-point vs floating-point DSP aur IEEE-754 floating point). Ek PID step $3$ multiplies $+ 2$ adds $= 5$ float ops hai. Version A float use karta hai (hardware, $\approx 3$ cycles each). Version B galti se double use karta hai (software emulation, $\approx 40$ cycles each). Compare karo.

Forecast: accidental double version kitne times slow hai?

Version A (float): $5 \times 3 = 15$ cycles. Yeh step kyun? Har single-precision op silicon mein ~3 cycles mein run hoti hai.
Version B (double): $5 \times 40 = 200$ cycles. Yeh step kyun? M4F FPU sirf 32-bit hai; har 64-bit double op silently ek software routine call karta hai — FPU unused baitha rehta hai. Yeh parent ka " $3.14$ vs $3.14 f$ " trap hai.
Slowdown ratio: $200/15 = 13. \overline{3} \times$ . Yeh step kyun? Exam chahta hai ki aap notice karo ki ek missing f suffix se silent $\sim 13 \times$ penalty aati hai.

Answers: A $= 15$ cycles, B $= 200$ cycles, ratio $\approx 13.3 \times$ .

Verify: $15 \times 13. \overline{3} = 200$ . ✓ Fix: 3.14f likho aur sinf call karo, sin nahi. Sirf M7 optional double-precision hardware offer karta hai.

Ex 8 — Cell K: deep pipeline misprediction (exam twist)

Worked example Mispredicted branch ka effective cost: M0 (2-stage) vs M7 (6-stage)

Branch misprediction CPU ko force karti hai ki partially-filled pipe discard kare aur refill kare. Refill penalty $(N - 1)$ cycles hai (wohi fill tax, phir se pay karo). Ek branchy ISR $30$ baar mispredict karta hai. M0 ( $N = 2$ ) vs M7 ( $N = 6$ ) par wasted cycles compare karo.

Forecast: kya "faster" M7 yahan zyada ya kam cycles waste karta hai?

M0 penalty per miss: $N - 1 = 2 - 1 = 1$ cycle. Total $= 30 \times 1 = 30$ cycles. Yeh step kyun? Shallow pipe almost instantly refill hoti hai — sirf 1 stage reload karna hai.
M7 penalty per miss: $N - 1 = 6 - 1 = 5$ cycles. Total $= 30 \times 5 = 150$ cycles. Yeh step kyun? Deep pipe mein 5 stages ka in-flight work discard aur reload karna tha — depth branchy code ke liye ek liability hai.
Ratio: $150/30 = 5 \times$ zyada wasted cycles M7 par per misprediction burst. Yeh step kyun? Yahi parent ki warning hai: "zyada stages hamesha faster nahi hota." Deep pipelines (dekho Pipelining and superscalar execution) clock speed khareedte hain, free IPC nahi — aur woh unpredictable branches par haarte hain.

Answers: M0 $30$ cycles waste karta hai, M7 $150$ cycles waste karta hai, ratio $5 \times$ .

Verify: Penalty $(N - 1)$ ke saath linearly scale karta hai: M7/M0 $= (6 - 1) / (2 - 1) = 5$ . ✓ Computed $150/30 = 5$ se match karta hai. Lesson: chhote, branchy, GPIO-poking control code ke liye, 2-stage M0+ ek M7 se zyada deterministic ho sakta hai.

Recall

Do :::

Cells-covered

A (Ex1), B (Ex2), C+D (Ex3), E+F (Ex4), G+H (Ex5), I (Ex6), J (Ex7), K (Ex8)

2-stage pipe par

I = 6

ke liye one-pass cycles

(2 - 1) + 6 = 7

1000 passes

1000 \times

one pass kyun nahi hota

fill tax

(N - 1)

sirf ek baar pay hota hai

Dual-issue core ki max IPC

w = 2

(at

p = 1

)

double M4F par slow kyun hai

uska FPU single-precision only hai, toh double software emulation par fall back karta hai

Deep pipelines branchy code ko kyun hurt karte hain

misprediction refill penalty

(N - 1)

cycles hai — bada

N

, bada waste