Microcontroller architecture — ARM Cortex-M series (M0, M3, M4, M7): Question bank

5.5.1 · D5 · Coding › Embedded Systems & Real-Time Software › Microcontroller architecture — ARM Cortex-M series (M0, M3,

Shuru karne se pehle, teen words jo is page mein baar baar aate hain, simple language mein:

True or false — justify karo

M4 mein FPU hai, isliye usmein double (64-bit) math hardware mein run hoti hai.

False. M4 FPU sirf single-precision (32-bit) hai, toh har double silently slow software emulation par fall back kar jaati hai — dekho IEEE-754 floating point ki wajah se 64-bit ek alag format kyun hai.

Ek 6-stage pipeline (M7) hamesha kisi bhi program ko 2-stage pipeline (M0) se kam cycles mein finish karta hai.

False. Deep pipes higher clock speed kharidti hain, free IPC nahi; branchy code par badi misprediction aur fill penalties deep pipe ko zyada cycles waste karaati hain har branch par. Dekho Pipelining and superscalar execution.

Ek ideal (no-stall) pipeline par, average cycles-per-instruction kitne bhi stages hon, 1 ke kareeb aa jaata hai.

True. Extra

(N - 1)

fill cycles ek baar pay hote hain; jaise instruction count badhta hai wo average out ho jaate hain, toh kisi bhi fixed

N

ke liye IPC → 1.

Superscalar (dual-issue) ka matlab hai M7 hamesha har cycle mein do instructions execute karta hai.

False. Woh up to do issue karta hai; sirf wo pairs jo no dependency rakhte hain aur sahi resources available hain co-issue hoti hain, toh real IPC roughly

1 + p

hota hai jahan

p \approx 0.3

–

0.5

, 2 nahi.

"Vectored" interrupts ka matlab hai CPU ek software loop chalata hai sahi handler jaldi dhundhne ke liye.

False. Vectored ka matlab hai har interrupt ka apna table slot hota hai, toh hardware seedha handler par jump karta hai bina kisi dispatch loop ke — dekho Interrupts and the NVIC.

NVIC par automatic register stacking ki wajah se ek plain C function interrupt handler ban sakta hai.

True. Hardware khud R0–R3, R12, LR, PC, xPSR push karta hai, toh tumhe state save karne ke liye assembly stub ki zarurat nahi, jo latency jitter ka ek source bhi khatam karta hai.

M7 mein cache add karne se uski execution timing zyada deterministic ho jaati hai.

False. Hit fast hoti hai lekin miss slow, toh runtime data-dependent ho jaata hai — worst-case analysis ke liye worse; isliye real-time code aksar TCM mein rehta hai instead.

Memory-mapped I/O ka matlab hai GPIO ko special "in/out" CPU instructions chahiye.

False. Iska matlab ulta hai: peripherals ordinary addresses par rehte hain, toh normal load/store instructions untak pahunch jaati hain — dekho Memory-mapped I/O and GPIO.

Determinism ke liye interrupt latency zero hona zaroori hai.

False. Determinism ke liye latency bounded aur knowable honi chahiye (

L_{m a x} = t_{detect} + t_{stack} + t_{higher-prio busy}

); har term nonzero hai lekin computable hai.

MPU (Memory Protection Unit) aur cache ek hi cheez hai.

False. Memory Protection Unit (MPU) address ranges par permissions check karta hai (kya yeh code yahan likh sakta hai?); cache memory ki ek speed copy hai. Bilkul alag kaam.

Error dhundho

"Humne compiler mein -mfloat-abi=hard enable kiya, toh runtime par FPU definitely on hai."

Error: compiler flags sirf FP instructions generate karte hain; tumhe startup par CPACR register mein CP10/CP11 bits bhi set karne padte hain, warna pehla FP instruction HardFault ki tarah trap karega.

"FIR filter pe faster jaane ke liye humne 120 MHz par M3 choose kiya 100 MHz ke M4 ke upar."

Error: M4 ek instruction mein multiply-accumulate karta hai (MLA, ya SIMD SMLAD se ek baar mein do), toh DSP par per cycle jeetta hai; M3 ki clock edge rarely 2–4× per-MHz gap band karti hai. Dekho Fixed-point vs floating-point DSP.

"Hamara RTOS har task ko MSP par chalata hai toh kernel aur tasks ek stack share karte hain."

Error: tasks PSP (Process Stack Pointer) par chalne chahiye jabki handlers MSP use karein, toh ek task apna stack overrun karke kernel corrupt nahi kar sakta — dekho RTOS task scheduling and context switching.

"10 instructions ki 1000-iteration loop ka cost

1000 \times 12 = 12000

cycles hai kyunki har pass mein 3-stage pipe fill hoti hai."

Error: pipe ek baar fill hoti hai, har pass mein nahi; cost hai

(3 - 1) + 10000 = 10002

cycles kyunki instructions iterations ke across continuously stream karte hain.

"M4F par humne sin() aur double PID ke liye use kiya kyunki floats precision kho dete hain."

Error: sin() aur double M4F par software emulation se hote hain; tum hardware FPU throw away kar rahe ho. Actually silicon hit karne ke liye sinf() aur float literals jaise 3.14f use karo.

"Humne pipeline bilkul hata di toh timing perfectly deterministic hai."

Error: pipeline determinism destroy nahi karta — uske fill/stall costs knowable hain. Real determinism killers cache misses jaisi unbounded features hain, fetch/decode/execute ka overlap nahi.

Why questions

ARM ek universal core ki jagah family (M0/M3/M4/M7) kyun bechta hai?

Kyunki embedded needs ek $0.20 pin-toggler (sabse sasta/lowest-power M0 chahiye) se lekar ek camera FFT pipeline (cached high-clock M7 chahiye) tak hoti hain; koi ek design power, area, aur throughput mein ek saath optimal nahi ho sakta.

M7 mein 6th pipeline stage kyun add ki gayi agar IPC phir bhi 1 ke taraf tend karta hai?

Har stage mein choti logic let karti hai chip ko zyada clock karne mein (zyada MHz), toh total work-per-second badhta hai chahe per-cycle throughput na badhe — depth clocks kharidti hai, IPC nahi.

Do stack pointers (MSP aur PSP) kyun hain?

Faults isolate karne ke liye: har RTOS task ka apna PSP stack hota hai jabki interrupts shared MSP par chalta hai, toh ek task ka stack overflow kernel ya handler state overwrite nahi kar sakta.

"Ek fixed cycle count mein automatic 8-register stacking" real-time ke liye itna important kyun hai?

Kyunki ek fixed, knowable stacking cost worst-case interrupt latency computable banata hai, jo exactly woh determinism hai jis par real-time deadlines depend karti hain.

Chhoti interrupt code par shallow 2-stage M0+ zyada M7 se deterministic kyun ho sakta hai?

Chote branchy handlers M7 ki deep-pipe fill aur branch-misprediction penalties suffer karte hain; M0+ mein aise penalty nahi hai, jo tighter aur zyada predictable timing deta hai.

SIMD (SMLAD) FIR filter cycles ko plain MLA ke comparison mein roughly half kyun karta hai?

SIMD do 16-bit multiply-accumulates ko ek 32-bit instruction mein pack karta hai, toh ek instruction do ka kaam karta hai — dekho Fixed-point vs floating-point DSP.

Edge cases

Agar tum M4F par floating-point instruction execute karo CP10/CP11 enable karne se pehle toh kya hoga?

CPU ke paas coprocessor ki permission nahi hai, toh instruction calculate karne ki jagah HardFault ki tarah trap karti hai — ek classic "FPU present but disabled" boot bug.

Jab kisi critical loop ka data M7 cache mein fit nahi karta toh timing ka kya hota hai?

Tumhein cache misses aane lagte hain, toh per-access time badh jaata hai aur data-dependent ho jaata hai; fix hai us hot code/data ko TCM mein rakhna guaranteed single-cycle access ke liye.

Degenerate case: ek

N

-stage pipeline par exactly ek instruction wala program kitne cycles leta hai, aur kyun 1 nahi?

Iska cost

N

cycles hai, kyunki us single instruction ko phir bhi complete hone ke liye saare

N

stages se guzarna padta hai — "1 per cycle" figure sirf tabhi hold karta hai jab pipe already full ho.

Limiting case: M7 par co-issuable pairs ka fraction

p \to 0

ho jaaye toh IPC kya ban jaata hai?

IPC

\to 1 + p (w - 1) = 1

; jab koi bhi pair co-issue nahi kar sakta, dual-issue koi benefit nahi deta aur core single-issue machine ki tarah behave karta hai. Dekho Pipelining and superscalar execution.

Edge case: ek lower-priority interrupt fire karta hai jab ek higher-priority handler chal raha hai — kya woh immediately run karta hai?

Nahi; woh wait karta hai (

t_{higher-prio busy}

term), lekin NVIC phir bhi use record karta hai aur baad mein run karta hai, aur ek higher-priority IRQ nesting ke zariye preempt karega — dekho Interrupts and the NVIC.

Edge case: tumne ek MPU region ko read-only set kiya, phir tumhara code uspe write karta hai. Kya hota hai?

Memory Protection Unit (MPU) write reject karta hai aur ek fault raise karta hai, bug ko illegal access ke moment par hi pakadta hai rather than silent corruption ko phailne dene ki jagah.

Boundary: kya cache hit ka latency deterministic hai?

Hit fast aur roughly fixed hoti hai, lekin tum guarantee nahi kar sakte ki har access hit hai, isliye access as a whole non-deterministic rehti hai — worst-case mein miss assume karna padta hai.

Recall Quick self-test

M4 FPU konsi precision hardware mein handle karta hai? ::: Sirf Single-precision (32-bit); double software par fall back karta hai. Deeper pipeline primarily kya kharidti hai? ::: Higher clock speed, higher IPC nahi. Determinism ka matlab hai latency kya hai? ::: Bounded aur knowable — zero nahi.