Noesis
4.1.12Computer Architecture (Deep)

Write policies — write-through, write-back, write-allocate

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🇮🇳 Yeh note Hinglish mein padho →

WHY do we even need a policy?

The two design pressures:

  • Speed: writing to main memory (DRAM) is ~100× slower than writing to the cache (SRAM). We want to avoid memory writes.
  • Correctness/Simplicity: memory should eventually match. The longer we delay, the more bookkeeping (dirty bits) we need.

Policy 1 — On a write HIT

The dirty bit — WHAT and WHY

Each cache line gets one extra bit.

  • dirty = 0: cache copy == memory (clean). On eviction, just discard — no memory write.
  • dirty = 1: cache copy was modified. On eviction, you must write the whole block back first.

This is why write-back needs the dirty bit and write-through does not (memory is never behind).

Policy 2 — On a write MISS

The block we want to write isn't in cache. Two choices:

Figure — Write policies — write-through, write-back, write-allocate

HOW it works — step by step

Write HIT

Policy Action
Write-through Write cache and memory. (often via a write buffer so CPU doesn't stall)
Write-back Write cache only, set dirty=1.

Write MISS

Combination Action
Write-allocate Read block from memory → cache, then write into cache.
No-write-allocate Write value to memory only; cache unchanged.

Eviction of a block (write-back only)

  • If dirty=1: write entire block back to memory, then load new block.
  • If dirty=0: just overwrite — no memory write.

Deriving the cost — from first principles

Worked examples

Common mistakes

Flashcards

Write-through writes to memory
on every write (cache and memory updated together).
Write-back writes to memory
only when a dirty block is evicted.
What bit does write-back require per line and why
the dirty bit, to know if memory is stale and needs writing on eviction.
Does write-through need a dirty bit
No — memory is always current.
Write-allocate vs no-write-allocate apply on a
write MISS.
Write-allocate action on a write miss
fetch the block into cache, then write it (treat as hit).
No-write-allocate action on a write miss
write directly to memory, don't cache the block.
Most common modern pairing
write-back + write-allocate.
Common simple pairing
write-through + no-write-allocate.
Average write cost write-through
tc+tmt_c + t_m.
Average write cost write-back
tc+m tm(1+d)t_c + m\,t_m(1+d) where mm=miss rate, dd=dirty-eviction fraction.
Why is write-back faster for hot loops
repeated writes hit cache; the slow tmt_m is only paid at rate mm (eviction), not per write.
Best policy for a memset you never read back
no-write-allocate (avoids useless block fetch).
What hides write-through latency from the CPU
a write buffer.
On clean-block eviction in write-back, memory is
untouched (just discard the copy).
Recall Feynman: explain to a 12-year-old

Imagine your notebook (cache) is a copy of the class textbook (memory). When the teacher changes a fact, you can either immediately run and edit the textbook too (write-through — safe but lots of running) or just fix your notebook now and mark the page with a sticky note (write-back — the sticky note is the dirty bit). You only bother walking to fix the textbook when you need that notebook page for something else (eviction). And if a fact is brand-new and not in your notebook (a write miss), you decide: copy the whole page into your notebook first (write-allocate) because you'll probably use it again, or just scribble it straight into the textbook and don't bother (no-write-allocate) if it's a one-time thing.

Connections

  • Cache Memory Fundamentals — tags, index, blocks, hit/miss.
  • Cache Replacement Policies — eviction (LRU/random) is when write-back flushes dirty data.
  • Cache Coherence — MESI — write policies underlie the M (Modified=dirty) state across cores.
  • Write Buffers and Store Buffers — how write-through hides memory latency.
  • Memory Hierarchy and AMAT — TwbT_{wb}, TwtT_{wt} feed into average memory access time.
  • DMA and I/O Consistency — why stale dirty cache lines must be flushed before DMA reads.

Concept Map

solves

answers on hit

answers on miss

option A

option B

requires

triggers write on

faster via

option A

option B

pairs with

pairs with

Write policy

Consistency problem: cache copy vs memory

Write HIT policy

Write MISS policy

Write-through: update cache and memory

Write-back: update cache only

Dirty bit

Eviction

Locality: repeated writes

Write-allocate: fetch block first

No-write-allocate: write to memory

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, cache main memory ka ek chhota fast copy hota hai. Read karna easy hai, problem write par aati hai — kyunki write ke baad cache ki copy aur memory ka data alag (mismatch) ho sakta hai. Write policy basically rule hai ki yeh mismatch kaise handle karein.

Pehla sawaal: write HIT par. Write-through matlab har write pe cache aur memory dono update — safe hai, lekin DRAM slow hota hai, toh har baar slow write padta hai. Write-back matlab sirf cache update karo aur ek dirty bit = 1 set kar do (matlab "yeh page badla hua hai"). Memory ko update tabhi karte ho jab woh dirty block cache se nikalna (evict) padta hai. Loops mein same variable baar-baar likhte hain, isliye write-back kai writes ko ek hi memory write mein collapse kar deta hai — bahut fast.

Doosra sawaal: write MISS par (block cache mein hai hi nahi). Write-allocate matlab pehle pura block memory se cache mein le aao, phir likho — locality ka faida. No-write-allocate matlab seedhe memory mein likh do, cache mein dalo hi mat — agar woh data dobara nahi padhna (jaise memset se array initialize karna), toh fetch karna waste hai.

Yaad rakho do alag axes hain: HIT pe through-ya-back, MISS pe allocate-ya-no-allocate. Real CPU mostly write-back + write-allocate use karte hain (kam memory traffic), aur simple systems write-through + no-write-allocate. Isiliye yeh topic important hai — yahi cache coherence (MESI ka Modified state) aur performance ki neev hai.

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Connections

Replacement policies — LRU, LFU, FIFO, RandomCoding · 4.1.11Cache coherence — MESI protocol in multicoreCoding · 4.1.13Memory hierarchy — registers, cache (L1 - L2 - L3), RAM, SSD, HDD — speed - size trade-offsCoding · 1.1.9Cache organization (direct-mapped)Hardware · 5.4.2Set-associative and fully associative cachesHardware · 5.4.3Cache line size and tagsHardware · 5.4.4Multi-level cache hierarchy (L1 - L2 - L3)Hardware · 5.4.8