Registers — general purpose, special (PC, SP, LR, CPSR)

4.1.5 · Coding › Computer Architecture (Deep)

Registers exist HI KYUN karte hain?

WHAT hai ek register, precisely?

HOW many bits? $W$ bits wala register $2^{W}$ distinct values store kar sakta hai.

32-bit register → $2^{32} \approx 4.29 \times 1 0^{9}$ values.
64-bit register → $2^{64} \approx 1.84 \times 1 0^{19}$ values.

Dono families

1. General-Purpose Registers (GPRs)

WHY general? Flexibility — compiler decide karta hai ki har register kya hold kare, isliye woh aapki hottest variables ko registers mein rakh sakta hai (yahi register allocation hai).

2. Special-Purpose Registers

Inki hardware-defined meaning hoti hai. CPU khud inhe read/update karta hai.

Reg	Name	Kya hold karta hai	Kyun special hai
PC	Program Counter	next instruction ka address jo fetch karna hai	Hardware har fetch par auto-increment karta hai; branches ise overwrite karte hain
SP	Stack Pointer	stack ke top ka address	Hardware (push/pop, call/ret) ise bump karta hai
LR	Link Register	function call ka return address	`BL` ise likhta hai taaki callee jaane kahan wapas jaana hai
CPSR	Current Program Status Register	condition flags + mode bits	ALU flags set karta hai; branches inhe read karte hain

Figure — Registers — general purpose, special (PC, SP, LR, CPSR)

PC — Program Counter (fetch loop derive karte hue)

First principles se increment derive karna. Maano instructions fixed width $L$ bytes ki hain (ARM: $L = 4$ ). Address $P C$ par instruction fetch karne ke baad, default next instruction yahan hogi: $P C_{next} = P C + L$ Hardware yeh current instruction execute hone se pehle karta hai, isliye jab tak instruction run hoti hai, PC agli wali ko point kar raha hota hai. Yahi wajah hai ki classic ARM par PC current + 8 read karta hai (pipeline: fetch do stages aage hoti hai) — ek famous gotcha.

Branch to target $T$ simply $P C \leftarrow T$ karta hai. Signed offset $o$ (instructions mein) wala relative branch compute karta hai: $P C \leftarrow P C_{ref} + L \cdot o$

SP — Stack Pointer (push/pop derive karte hue)

Zyaadatar CPUs full-descending stack use karte hain: stack lower addresses ki taraf grow karta hai, aur SP last pushed item (occupied top) ko point karta hai.

Value $v$ ka PUSH derive karna (full-descending, word = 4 bytes):

Top ko niche le jaake jagah banao: $S P \leftarrow S P - 4$ . Why first? Taaki hum current top item ko overwrite na karein.
Store karo: $Mem [S P] \leftarrow v$ .

Register $r$ mein POP derive karna:

Current top padho: $r \leftarrow Mem [S P]$ .
Slot free karo: $S P \leftarrow S P + 4$ . Why after? Data pehle read hona chahiye, tabhi hum slot free declare karein.

LR — Link Register (call/return derive karte hue)

Function call BL target (Branch with Link) atomically do kaam karta hai: $L R \leftarrow P C_{next} P C \leftarrow t a r g e t$ PC_next kyun save karte hain, PC nahi? Kyunki hum call ke baad wali instruction par resume karna chahte hain, call ko dobara run nahi karna (infinite loop!).

Return karne ke liye: BX LR karta hai $P C \leftarrow L R$ .

CPSR — flags (conditional branches derive karte hue)

Flags exist HI KYUN karte hain? Branches ko poochna padta hai "kya result zero tha? negative?" bina dobara compute kiye. Compare instruction CMP a, b $a - b$ compute karta hai, result throw away karta hai, lekin flags rakhta hai. Phir BEQ (branch if equal) sirf $Z$ test karta hai.

CMP a,b ke baad BEQ derive karna:

CMP $a - b$ compute karta hai. Agar $a = b$ toh $a - b = 0$ → $Z = 1$ .
BEQ branch karta hai iff $Z = 1$ → branch karta hai iff $a = b$ . ✔ first-principles se correct.

V (signed overflow) first principles se derive karna. $n$ -bit signed numbers ke saath addition $r = a + b$ ke liye, signed overflow tab hota hai jab dono operands ka sign same ho lekin result ka sign opposite ho: $V = (sign_{a} = sign_{b}) \land (sign_{r} \neq = sign_{a})$ Kyun? Do positives legitimately negative mein sum nahi ho sakte range ke andar; agar bit pattern kehta hai unhone kiya, toh true sum representable range $[- 2^{n - 1}, 2^{n - 1} - 1]$ se overflow hua.

Worked example Nested call wale function mein ek local jo survive karta hai

sum3:          ; sum3(a in R0, b in R1, c in R2)
  PUSH {R4, LR}   ; save LR (we will call helper) + a callee-saved reg
  ADD  R4, R0, R1 ; R4 = a+b   (R4 must survive the BL)
  ...             ; BL helper  ; this clobbers LR & R0–R3
  ADD  R0, R4, R2 ; R0 = (a+b)+c   ← R4 still intact because we didn't trust it to a scratch reg
  POP  {R4, PC}   ; restore R4, and pop saved-LR straight into PC = return

LR push kyun karo? BL helper ise overwrite karta hai. PC mein pop kyun karo, LR mein nahi? POP {…, PC} directly PC load karta hai = ek instruction mein return (efficient).

Recall Feynman: 12-saal ke bachche ko explain karo (click to reveal)

CPU ek super-fast cook hai. Registers woh kuch bowls hain jo chopping board ke bilkul paas hain — cook ingredients unse instantly uthata hai. RAM woh bada fridge hai kitchen ke us paar: bahut jagah, lekin wahan jaana slow hai. Kuch bowls special hain: ek bowl (PC) ek sticky note hold karta hai jisme likha hai "next step number." Doosra (SP) dirty plates ke stack ka top mark karta hai. Teesra (LR) ek note hai jisme likha hai "is kaam ke baad, yahan wapas aao." Aur CPSR ek chota scoreboard hai: kya last result zero tha? negative? kya woh edge se spill hua? Cook woh scoreboard check karta hai decide karne ke liye ki recipe mein aage skip karna hai ya nahi.

Common mistakes

Flashcards

Registers RAM se faster kyun hote hain?

Yeh physically CPU die par hote hain, seedha ALU se wired; koi off-chip memory bus latency nahi (~1 cycle vs ~100+ cycles).

Ek general-purpose register ko special se kya alag karta hai?

GPR ki koi hardware-imposed meaning nahi hoti (compiler decide karta hai iska use); ek special register (PC/SP/LR/CPSR) ka ek fixed role hota hai jise hardware khud read/update karta hai.

PC kya hold karta hai aur har cycle mein kaise change hota hai?

Next instruction ka address; hardware har fetch par

P C \leftarrow P C + L

(

L

=instruction length) karta hai, aur branches ise target se overwrite karte hain.

Full-descending stack mein PUSH kya karta hai?

S P \leftarrow S P - 4

phir

Mem [S P] \leftarrow v

(pehle decrement, phir store).

Full-descending stack mein POP kya karta hai?

r \leftarrow Mem [S P]

phir

S P \leftarrow S P + 4

(pehle read, phir free).

BL target kaunse do actions perform karta hai?

L R \leftarrow P C_{n e x t}

(return address save karo) aur

P C \leftarrow t a r g e t

(jump karo).

Non-leaf function ko LR kyun save karna chahiye?

Ek nested BL LR overwrite karta hai, caller ka return address destroy karta hai; LR ko stack par save karne se unlimited nesting possible hoti hai.

Char CPSR condition flags kaunse hain?

N (negative, MSB=1), Z (zero result), C (carry/borrow, unsigned), V (signed overflow).

Addition par V (signed overflow) flag ka rule batao.

V=1 iff dono operands ka same sign ho lekin result ka opposite sign ho.

CMP a, b ke baad, BEQ kaun sa flag test karta hai aur kyun?

Z test karta hai; CMP

a - b

compute karta hai, isliye

Z = 1

exactly tab hota hai jab

a = b

8-bit signed 0x7F + 0x01 ke liye N,Z,C,V kya hain?

N=1, Z=0, C=0, V=1 (127+1 signed range se overflow ho kar −128 ban jaata hai).

ARM par kaun si instructions flags update karti hain?

Sirf S-suffixed ops (ADDS, SUBS, …) aur CMP/CMN/TST/TEQ; plain ADD nahi karta.

Connections

Instruction Cycle (Fetch-Decode-Execute) — PC fetch stage drive karta hai.
The Stack and Function Calls (Calling Conventions) — SP & LR call/return frames implement karte hain.
Pipelining — classic ARM "PC = current + 8" offset explain karta hai.
Two's Complement Arithmetic — define karta hai ki N/C/V flags kaise compute hote hain.
Addressing Modes — registers as operands vs memory operands.
Cache Memory Hierarchy — registers L1 ke upar sabse fast tier hain.