Von Neumann architecture — components, bottleneck: Worked examples

We reuse exactly two tools from the parent. Let us re-state them in plain words so nothing is assumed.

The scenario matrix

Every problem this topic can pose is one (or a blend) of these cells. Each worked example below is tagged with the cell it covers.

Cell	What makes it special	Where it bites
A. Ordinary	Plain numbers, $d > 0$ , finite $t_{m}$	Engine 1 & 2 straight up
B. Zero data ( $d = 0$ )	Instruction touches no operands (e.g. `NOP`, register-only op)	$T = 1$ , pure fetch limit
C. Heavy data ( $d$ large)	Instruction is mostly memory traffic	fetch term becomes negligible
D. Degenerate memory ( $t_{m} \to \infty$ )	Memory infinitely slow vs CPU	$U \to 0$ — the bottleneck in the limit
E. Degenerate CPU ( $t_{m} \to 0$ )	Memory instant / perfect cache	$U \to 1$ — bottleneck vanishes
F. Cache fix	Weighted hit/miss average access	Engine "bonus"
G. Word problem	Real story, you must extract $B, d, t_{c}, t_{m}$	translation skill
H. Exam twist	Compare Von Neumann vs Harvard, or solve backwards for a target	multi-step reasoning

The nine examples below fill all eight cells (A–H), with A and H visited twice.

Figure — Von Neumann architecture — components, bottleneck

Example 1 — Cell A (ordinary throughput)

Example 2 — Cell B (zero data accesses, $d = 0$ )

Example 3 — Cell C (data-heavy, $d$ large)

Example 4 — Cell D (memory infinitely slow, limiting behaviour)

Example 5 — Cell E (memory instant, the other limit)

Example 6 — Cell F (the cache fix, weighted average)

Worked example Hiding the wall with a cache

95% of accesses hit a fast cache ( $t_{hit} = 2$ ns); 5% miss to slow memory ( $t_{miss} = 40$ ns). Find average access time $\overset{ˉ}{t}$ , and the speedup over always-miss.

Forecast: will $\overset{ˉ}{t}$ be closer to 2 or to 40? (Closer to 2 — misses are rare.)

Probabilities: $p_{hit} = 0.95$ , $p_{miss} = 1 - 0.95 = 0.05$ . Why this step? Miss and hit are the only outcomes, so they sum to 1.
Weighted average: $\overset{ˉ}{t} = 0.95 (2) + 0.05 (40) = 1.9 + 2.0 = 3.9$ ns. Why this step? Bonus engine — each access time weighted by how often it happens.
Speedup vs always-miss: $\frac{40}{3.9} \approx 10.3 \times$ . Why this step? Old cost ÷ new cost.

Verify: $\overset{ˉ}{t} = 3.9$ ns sits between $2$ and $40$ (a valid average must). ✓ The cache didn't touch the bus or main memory — it hid the bottleneck, exactly the parent's point that caching is mitigation, not a redesign. Main memory is still unified → still Von Neumann. ✓

Example 7 — Cell G (word problem, extract the numbers)

Worked example The story you must decode

"A sensor logger runs a loop. Each pass fetches 1 instruction and, on average, reads 3 samples and writes 1 average back to memory. The memory bus can transfer 800 million words per second. The vendor claims 1 billion loop-passes per second. Is that possible?"

Forecast: vendor claims 1e9 with only 8e8 words/s of bus — smells too good. Let's check.

Extract $B$ : "800 million words/s" → $B = 8 \times 1 0^{8}$ words/s. Why this step? Identify the bus throughput from the words in the story.
Extract $d$ : 3 reads + 1 write $= 4$ data words → $d = 4$ . Why this step? Every operand and result crosses the shared bus in a Von Neumann machine.
Cost: $T = 1 + 4 = 5$ words/pass. Why this step? Fetch + 4 data.
Max passes/s: $\frac{8 \times 1 0 ^{8}}{5} = 1.6 \times 1 0^{8}$ passes/s. Why this step? Engine 1.

Verify: $1.6 \times 1 0^{8} ≪ 1 \times 1 0^{9}$ . The claim is impossible on this bus — it exceeds the ceiling by ~6×. ✓ To hit 1e9 you'd need $B \geq 5 \times 1 0^{9}$ words/s, i.e. a much fatter data bus.

Example 8 — Cell H (exam twist: Von Neumann vs Harvard)

Worked example Same memory, different structure

One bus of $B = 4 \times 1 0^{9}$ words/s. Instructions average $d = 1$ data word. (a) Von Neumann: instruction and data share the one bus. (b) Harvard: separate instruction bus and data bus, each $4 \times 1 0^{9}$ words/s, so fetch and data-access happen in parallel. Find $IPS_{m a x}$ for each and the ratio.

Forecast: two parallel buses vs one shared — guess the speedup. (For $d = 1$ , exactly 2×.)

Von Neumann: $T = 1 + 1 = 2$ , so $IPS = \frac{4 \times 1 0 ^{9}}{2} = 2 \times 1 0^{9}$ . Why this step? One shared bus carries both the fetch and the 1 data word → they serialize.
Harvard: the fetch (1 word) rides the instruction bus while the data word rides the data bus — simultaneously. Per-instruction time is set by the busier bus: $max (1, 1) = 1$ word-time. So $IPS = \frac{4 \times 1 0 ^{9}}{1} = 4 \times 1 0^{9}$ . Why this step? Parallel paths → the two transfers overlap; throughput is limited by the heavier lane, not their sum.
Ratio: $\frac{4 \times 1 0 ^{9}}{2 \times 1 0 ^{9}} = 2 \times$ . Why this step? New ÷ old.

Verify: the only thing that changed was the structure (one shared channel → two parallel channels), not the memory speed — proving the parent's "the bottleneck is structural, not just slowness" point. ✓ For $d = 1$ the shared bus does 2 word-times, the split buses do 1, hence exactly 2×. ✓

Worked examples — Von Neumann architecture — components, bottleneck