Von Neumann architecture — components, bottleneck

4.1.1 · Coding › Computer Architecture (Deep)

YE design exist kyun karta hai?

Components KYA hain?

Figure — Von Neumann architecture — components, bottleneck

Ye program KA AISE run karta hai? (Fetch–Decode–Execute cycle)

Step by step (har step ke saath Ye step kyun?):

Fetch: PC mein address par instruction ko IR mein copy karo. Kyun? CPU ko instruction apne andar chahiye taaki usp act kar sake — memory itni door/slow hai ki wahan decode karna possible nahi.
PC ← PC + 1 (agli instruction ki taraf point karo). Abhi kyun? Pehle increment karo taaki agar instruction ek jump bhi ho, tab bhi "default next" ready ho; jumps sirf PC ko overwrite karte hain.
Decode: CU IR mein bits interpret karta hai (kaun sa operation? kaun se operands?). Kyun? Bits meaningless hain jab tak CU opcode ko control signals mein map nahi karta.
Execute: ALU/CU/memory action perform karte hain (add, load, store, branch). Kyun? Ye akela step hai jo machine ki state meaningfully change karta hai.
Repeat.

Bottleneck KYA hai? (headline result)

Ise quantify karte hain (first principles se derivation)

Hum effective throughput chahte hain. Maano:

Bus ek bus cycle mein ek word carry kar sakta hai.
Ek average instruction ko 1 fetch chahiye (instruction ke liye) + average $d$ data accesses (operands/results ke liye).

Tab memory transfers per instruction: $T = 1 + d (words)$

Agar bus $B$ words/second deliver karta hai, toh instructions/second limited hoti hain: $IPS_{m a x} = \frac{B}{T} = \frac{B}{1 + d}$

Utilisation idea: agar CPU ek instruction $t_{c}$ time mein compute kar sakta hai lekin memory ke liye $t_{m}$ time wait karna padta hai, toh useful work karne ka fraction hai: $U = \frac{t _{c}}{t _{c} + t _{m}}$ Jab memory relatively slow hoti jaati hai ( $t_{m} ↑$ ), $U \to 0$ . Woh girta hua $U$ hi bottleneck hai.

WORKED EXAMPLES

Steel-manned mistakes

Recall Feynman: ek 12-saal ke bachche ko samjhao

Socho ek chef (CPU) kitchen mein hai, aur ek tiny hallway (the bus) ek single pantry (memory) tak jaati hai. Us pantry mein tum recipe cards AUR ingredients dono rakhte ho. Khaana pakane ke liye, chef ko hallway se recipe card lene jaana padta hai, wapas aana padta hai, phir gajar ke liye dobara jaana padta hai, phir pyaaz ke liye dobara — ek baar mein ek hi trip, kyunki hallway mein sirf ek insaan fit hota hai. Chef kaat-ne mein bahut fast hai lekin poora din bhaagta rehta hai. Ek narrow hallway mein ye endless bhaagna hi Von Neumann bottleneck hai. Ek trick: chopping board ke bilkul paas favourite ingredients ki ek chhoti shelf rakhlo (ek cache) taaki zyaadatar time use hallway ki zaroorat hi na pade.

Active Recall

Von Neumann architecture ki defining feature kya hai?

Instructions aur data same memory mein store hote hain aur single shared bus par access kiye jaate hain.

Von Neumann machine ke paanch components ke naam batao.

Memory, Control Unit, ALU, Input/Output, aur (shared) Bus.

Von Neumann bottleneck kya hai?

Single shared memory/bus ek waqt mein sirf ek transfer allow karta hai, isliye CPU memory ka wait karte hue stall ho jaata hai, throughput limit ho jaati hai.

Instruction cycle ke steps kya hain?

Fetch → (PC increment) → Decode → Execute → repeat.

Fetch step mein kaun se do CPU registers kaam aate hain?

Program Counter (PC, next address hold karta hai) aur Instruction Register (IR, fetched instruction hold karta hai).

Bus-limited instruction rate ka formula?

IPS_max = B / (1 + d), jahan B = words/sec bus throughput aur d = avg data accesses per instruction.

(1+d) term mein "+1" kyun hai?

"1" instruction fetch ke liye hai; "d" average data words hain jo usse phir chahiye.

Harvard architecture bottleneck kaise avoid karta hai?

Ye instructions aur data ke liye alag memories aur buses use karta hai, isliye dono simultaneously access ho sakte hain.

Caches bottleneck ko kaise mitigate karte hain?

Ye frequently-used code/data CPU ke paas rakhte hain, isliye zyaadatar accesses slow shared path skip kar dete hain; effective time ≈ hit/miss times ka weighted average.

Agar t_c=1ns compute aur t_m=4ns wait hai, toh CPU utilisation kya hai?

U = t_c/(t_c+t_m) = 1/5 = 20%.

Kya split L1-I aur L1-D caches wala CPU "pure Harvard" hai?

Nahi — ye "modified Harvard" hai; main memory abhi bhi unified hai, isliye ye fundamentally Von Neumann hai.

Connections

Harvard Architecture — contrasting separate-bus design.
CPU Registers — PC, IR, accumulator jo cycle mein use hote hain.
Fetch-Decode-Execute Cycle — runtime loop.
Memory Hierarchy and Caching — main mitigation.
Buses (Address, Data, Control) — shared channel itself.
Stored Program Concept — historical foundation.
Instruction Set Architecture — IR mein bits ka matlab.