Radiation effects — TID, SEE, displacement damage: Question bank

This is a self-test page for the radiation effects topic. Every item below targets a specific trap — a place where the wording sounds right but the physics disagrees, or where a boundary case breaks the "usual" rule. Read each prompt, commit to an answer out loud, then reveal.

Before we start, three words we lean on constantly, in plain language:

A quick way to hold the three apart in your head: think of a chip as a house. TID is a water stain that spreads slowly across a ceiling over years; SEE is a single lightning strike that flips one switch in an instant; DD is a termite silently hollowing out a wooden beam. The figure below draws that three-way split so you can point to it while answering.

Figure — Radiation effects — TID, SEE, displacement damage

Six symbols this page leans on — earn them before you meet them

Several reveals below use compact notation. Here is each symbol in plain words, and why it exists, before you hit it in a question.

Definition The trapped-charge / threshold-shift chain (TID)

Picture a MOSFET as a metal gate plate sitting a tiny distance above a silicon channel, separated by a thin glassy insulator (the oxide, SiO₂). The gate voltage decides whether the channel conducts.

$t_{ox}$ — the oxide thickness: how far the gate sits above the channel (a few nanometres). Bigger $t_{ox}$ = gate is farther away.
$ϵ_{ox}$ — the oxide permittivity: a material constant saying how strongly SiO₂ passes an electric field through itself. It is what turns "geometry" into "capacitance".
$C_{ox} = \frac{ϵ _{ox}}{t _{ox}}$ — the oxide capacitance per unit area. This is just the parallel-plate rule "capacitance = permittivity ÷ plate gap": the gate and channel are two plates with the oxide between them. Thicker oxide (larger $t_{ox}$ ) means the plates are farther apart, so less capacitance.
$Q_{trap}$ — the sheet of positive charge trapped in the oxide after irradiation (the holes that got stuck).

Formula Why trapped charge shifts the threshold

The threshold voltage $V_{th}$ is the gate voltage at which the channel just turns on. Now drop a sheet of stuck positive charge $Q_{trap}$ into the oxide. That positive charge already pulls electrons toward the channel for free — it does part of the gate's job. So the external gate now needs less voltage to reach the same turn-on condition. The size of that free help is exactly "charge divided by the capacitance that charge sits on": $Δ V_{th} = - \frac{Q _{trap}}{C _{ox}}$ The minus sign says the shift is downward (turns on easier) for positive trapped charge. Substituting $C_{ox} = ϵ_{ox} / t_{ox}$ gives $Δ V_{th} = - Q_{trap} t_{ox} / ϵ_{ox}$ — note the thickness on top, so thick oxides drift far worse. This is the same $V = Q / C$ you meet with any capacitor; here $C$ is the oxide capacitance and $Q$ is the radiation-trapped charge.

True or false — justify

TID depends only on how much total energy the radiation dumps, regardless of what particle carried it

Roughly true for the ionizing part — TID is a lumped "energy deposited" number, so a proton and an electron that deposit the same dose cause similar TID. The catch: they may also cause very different displacement damage, which TID does not count.

A part rated "10 krad" will always survive up to exactly 10 krad and fail the instant it passes

False. The rating is a qualification floor with margin baked out, not a cliff. Real drift is gradual and part-to-part variable, which is exactly why engineers demand 2–3× margin instead of trusting the number.

Lowering the dose rate always makes TID damage less severe

False — this is the enhanced low-dose-rate sensitivity (ELDRS) trap. In some bipolar oxides a slower dose rate gives more damage, because the annealing that normally heals trapped charge can't keep up in a way that favours recovery. Slow can be worse.

A single cosmic ray can permanently destroy a chip

True. That's what SEL (latchup) and SEB/SEGR (burnout, gate rupture) are — one particle triggers a runaway current or ruptures a gate. Not every SEE is a harmless bit flip.

Error-correcting codes protect against all three damage mechanisms

False. EDAC fixes soft SEUs (bit flips) beautifully, but it does nothing for the slow threshold drift of TID or the permanent lifetime loss of displacement damage, and it cannot un-latch a latched-up chip.

Adding twice the aluminium shielding roughly halves the total dose

Roughly true for the softer part of the spectrum, but with sharply diminishing returns — going from 2.5 mm to 10 mm Al only cuts dose by about 2×, because the penetrating high-energy tail barely notices the extra metal. Shielding is not a linear knob.

Displacement damage matters most for logic gates

False. DD hurts minority-carrier devices — solar cells (Photovoltaic Systems), optocouplers, bipolar transistors, CCD/CMOS imagers — because it wrecks carrier lifetime. Digital CMOS logic is mostly a majority-carrier device and shrugs most DD off.

Smaller transistor nodes are more radiation-tolerant because there's less material to hit

False, and this is a classic trap. Smaller nodes have tiny node capacitance, so the critical charge

Q_{crit}

needed to flip a bit is tiny too — they're more SEU-prone per hit, even though each node is a smaller target.

Spot the error

"GEO is safer than LEO because it's above the Van Allen belts."

The error is "safer" in general. GEO sits at the outer electron belt and sees high TID from trapped electrons, plus the full galactic-cosmic-ray flux (no strong magnetic shielding), giving worse SEE. It dodges the intense inner-belt protons of LEO, but "above the belts = safe" is wrong.

"Since SEUs are random, you just install more RAM and average them out."

Adding memory adds more bits to be upset — the device upset rate scales with bit count. The fix is EDAC and scrubbing, not raw capacity. More cells means more error events, not fewer.

"TID is fixed by the mission's total fluence, so the solar cycle doesn't matter."

The solar cycle strongly modulates the trapped-electron population and the galactic-cosmic-ray flux (solar max suppresses GCR), so the dose rate and total accumulated TID both depend on when in the cycle you fly. Timing changes the answer.

"Latchup is just a fancy bit flip, so a reset clears it."

Latchup is a self-sustaining parasitic-thyristor conduction path drawing large current; a logic reset won't stop it. You must remove and re-apply power to break the latch — and if the current was high enough, the part is already dead.

"Cross-section

σ

is measured in cm² so it's the physical size of the chip."

σ

is an effective sensitive area per bit for upsets — it's the geometric cell area only at saturation (very high LET). Below the LET threshold it's zero, and in between it rises along the Weibull curve. It is a response measure, not a ruler.

"A part with a higher LET threshold is more sensitive to heavy ions."

Backwards. A higher

LET_{th}

means it takes a more ionizing particle to cause an upset, so fewer particles in the spectrum qualify — that's less sensitive, i.e. more robust.

"Protons don't cause SEUs because they're much lighter than heavy ions."

Direct proton ionization is weak, but protons cause upsets indirectly via nuclear reactions in the silicon that produce heavy recoil fragments, which then ionize densely. In proton-rich LEO this indirect channel dominates the SEU rate.

"The Weibull cross-section curve is just an arbitrary fitting trick with no meaning."

The Weibull curve is an S-shaped rising function (flat near zero, then a steep rise, then a plateau) used because measured upset cross-section really does behave that way versus LET: nothing below threshold, a rapid climb once particles start depositing enough charge, and a saturation at the cell's geometric area. The fit parameters (

LET_{th}

, width, shape) summarise that physical response in four numbers.

Why questions

Why does a positive trapped charge in the oxide shift the n-channel threshold negative?

The trapped positive charge sits above the channel and partly does the gate's job of attracting electrons, so a smaller (more negative shift) gate voltage already turns the device on — threshold drops, leakage climbs. This is the

Δ V_{th} = - Q_{trap} / C_{ox}

relation in words.

Why do holes cause the TID damage while electrons mostly don't?

In SiO₂ electrons are highly mobile and are swept out in nanoseconds, leaving nothing behind. Holes crawl and readily fall into defect sites near the interface, where they get trapped and stay — so the surviving charge is positive.

Why is displacement damage tied to "non-ionizing" energy loss when radiation is obviously energetic?

Because the metric that matters for DD is the energy that goes into knocking atoms off lattice sites (nuclear elastic collisions), not the energy spent making electron-hole pairs. That mechanically-relevant fraction is the NIEL, deliberately separated from ionization.

Why does the same orbit give different dose to two boxes on the same spacecraft?

Placement and local mass change the effective shielding geometry — a box buried behind other hardware sees a different attenuated spectrum than one on an outer panel. Dose is a local quantity, not a spacecraft-wide constant.

Why does modern triple-well CMOS resist latchup better?

Latchup needs the loop gain of the two parasitic bipolar transistors to exceed one (

α_{PNP} \cdot α_{NPN} > 1

). The extra well isolates the n-well from the substrate, breaking one leg of that feedback loop so the loop can't sustain itself.

Why do designers care about minority-carrier lifetime for DD but not for digital logic?

DD-created defects act as recombination centers that kill minority carriers, crippling devices (solar cells, bipolar, imagers) whose operation depends on those carriers surviving and diffusing. Digital switching rides on majority carriers, so it is far less affected.

Edge cases

At exactly zero shielding, is TID infinite?

No — it's finite but very high, set by the raw ambient flux integrated over the mission. Zero shielding just removes attenuation; the incoming spectrum is still a finite quantity, so the dose is large but bounded.

What happens to the SEE rate when a particle's LET is below

LET_{th}

The cross-section is zero: no matter how many such particles arrive, the deposited charge never reaches

Q_{crit}

, so they contribute nothing to the upset integral. Only particles above threshold count.

If two independent upsets hit the same protected word before scrubbing, what does single-error-correcting EDAC do?

A single-error-correct / double-error-detect code will detect the double error but cannot correct it — it flags an uncorrectable fault. This is exactly why scrubbing runs faster than upsets accumulate, to keep each word at zero or one error.

In the limit of a very slow, very low-energy proton, does it still cause displacement damage?

Only if its recoil transfer exceeds the displacement threshold energy (~21 eV in silicon). Below that, the struck atom just wobbles and returns to its site — no permanent defect. There is a hard floor beneath which DD simply doesn't happen.

For an extremely thick oxide, does the threshold shift grow without bound with thickness?

The trapped charge scales with thickness, and since

Δ V_{th} = - Q_{trap} / C_{ox}

with

C_{ox} = ϵ_{ox} / t_{ox}

, the shift grows roughly as

t_{ox}^{2}

— thicker oxides drift dramatically worse, which is one reason thin-oxide modern processes are inherently more TID-tolerant.

What is the SEU rate for a device flown deep inside a solid metal block far exceeding any cosmic-ray range?

It trends toward the rate set only by the penetrating GCR tail and secondary particles the shield itself generates — it never reaches exactly zero, because the highest-energy ions and their nuclear secondaries cannot be fully stopped by practical mass.

Recall One-line self-check

Which of the three mechanisms is (a) cumulative, (b) per-particle, (c) permanent-but-structural? ::: (a) TID, (b) SEE, (c) Displacement Damage.

See also: Reliability Engineering, Semiconductor Physics, Spacecraft Orbits.