6.5.4 · D1Advanced & Emerging Architectures

Foundations — High Bandwidth Memory (HBM - HBM2 - HBM3)

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This page assumes nothing. Before you read the parent note on High Bandwidth Memory, we build every word and symbol it leans on. Read top to bottom; each idea uses only the ones above it.


1. A "bit" and a "byte" — the units everything is counted in

Why the topic needs this: memory capacity and bandwidth are measured in bytes, but the actual hardware pushes bits down wires. Every time you see "divide by 8" later, it is because we are translating bits the wires carry into bytes we quote.


2. A "wire / pin" and what it means to "toggle"

Figure — High Bandwidth Memory (HBM - HBM2 - HBM3)

Look at the figure: each horizontal line is one wire. A wire that toggles quickly sends many bits per second; a wire that toggles slowly sends fewer. A single wire can never send two bits at the same instant — that is why we need many wires to move data fast.

Why the topic needs this: HBM's headline is "1024 wires." You cannot understand why width helps until you see that each extra wire is an independent lane carrying its own stream of bits.


3. The symbol — how many data wires


4. The symbol — per-pin transfer rate, and why "Gbps"

Figure — High Bandwidth Memory (HBM - HBM2 - HBM3)

The figure shows one clock wave (violet). With single data rate, one bit lands per full cycle. With double data rate (DDR), a bit lands on both the up-edge and the down-edge — twice the bits from the same clock. That is why "1 GHz DDR = 2 Gbps."


5. Putting them together — the bandwidth formula

See Memory Wall for why we are desperate to grow this number, and DDR vs GDDR vs HBM for how the two knobs are split differently across memory families.


6. Power per wire — the symbols , ,

Why the topic needs this: it explains HBM's superpower. HBM keeps its wires short (small , because they sit on a tiny carrier next to the chip), low-swing (small ), and slow (small ). Small , small , small → tiny per wire. Even with 1024 wires, the total stays low. This is measured as energy per bit (pJ/bit).


7. Why the wires can be short — the physical stack

Figure — High Bandwidth Memory (HBM - HBM2 - HBM3)

The figure is a side view. TSVs (magenta) run vertically through the DRAM dies. Microbumps drop the stack onto the interposer (orange), which sits beside the GPU/processor. Because both live on the same tiny tray, the data wires are millimetres long instead of the centimetres of a printed circuit board — that is the geometric reason is small.

Why the topic needs this: the formula in section 6 says short wires save power, but nothing physically forces wires to be short. TSVs + interposer are the machinery that makes them short. Compare with GDDR Memory, where chips sit far away on the board.


8. "N-Hi" and "channel" — counting height and independence


The prerequisite map

bit and byte

wire toggling

N wires count

f rate per wire

Bandwidth = N times f over 8

Power = C V squared f

TSVs and interposer

short wires small C

Why HBM wins wide and slow

N-Hi and channels

Read it as: units feed the bandwidth formula and the power formula; the physical stack makes wires short (small ); together they explain why HBM chooses wide + slow.


Equipment checklist

You are ready for the parent note when you can answer each of these out loud:

What is a bit, and what is a byte?
A bit is one on/off signal; a byte is 8 bits bundled.
Why do bandwidth formulas divide by 8?
To convert bits (what wires carry) into bytes (the quoted unit); 8 bits = 1 byte.
What does mean and what is its picture?
The number of parallel data wires — the number of highway lanes.
What does mean, and why is 1 GHz DDR equal to 2 Gbps?
is bits/s per wire; DDR sends a bit on both clock edges, doubling the effective rate.
Write the bandwidth formula and name each symbol.
; = wires, = per-wire bit rate, /8 = bits→bytes.
State the dynamic-power relation and what , , each mean.
; = wire capacitance, = voltage swing, = toggle rate.
Why does keeping wires short save power?
Short wires have small capacitance , and grows with .
What is a TSV, physically?
A copper via drilled vertically through a silicon die to connect stacked dies.
What is a silicon interposer, and what integration style does it enable?
A passive silicon tray carrying thousands of fine wires; enables 2.5D side-by-side integration.
What does "8-Hi" mean?
A stack 8 DRAM dies tall.
How can HBM3 have 16 channels but still a 1024-bit bus?
16 channels × 64 bits = 1024 data bits total.