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6.3.10 · D5 · HinglishInterconnects, Buses & SoC

Question bank — IP cores and SoC bus fabric

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6.3.10 · D5 · Hardware › Interconnects, Buses & SoC › IP cores and SoC bus fabric

Yeh page ek misconception hunter hai. Neeche har item mein ek claim, ek error, ek "why", ya ek boundary case diya gaya hai — sab parent note ke ideas ke baare mein. Prompt padho, apna jawab reveal karne se pehle zor se bolo, aur — yahi poora point hai — ensure karo ki tumhara reveal mein reasoning ho, sirf "true" ya "false" nahi.

Shuru karne se pehle, teen words jo hum baar baar use karenge. Ek master woh IP core hai jo transaction start karta hai (CPU data maang raha hai). Ek slave woh IP core hai jo respond karta hai (RAM jawab de raha hai). Arbitration woh referee logic hai jo winner pick karta hai jab kai masters ek hi slave ko ek saath access karna chahte hain. Neeche sab kuch sirf inhi teen ideas pe aur jo parent note ne build kiya, usi pe assume karta hai.

True ya false — justify karo

Ek "soft" IP core ko soft isliye kehte hain kyunki yeh hardware se slow hota hai.
False — "soft" malleability ko refer karta hai, speed ko nahi. Yeh synthesizable RTL (Verilog/VHDL) ke roop mein ship hota hai jise tum synthesis ke dauran kisi bhi process node ke liye reshape kar sakte ho, jaise clay; ek hard core ek fixed physical layout ke roop mein ship hota hai jise tum reshape nahi kar sakte.
Ek hard IP core tumhe process nodes retarget karne ki best flexibility deta hai.
False — yeh bilkul ulta hai. Ek hard core ek fixed GDSII layout hai jo ek specific process ke liye optimised hai, isliye yeh best performance/area deta hai lekin retargeting flexibility zero hoti hai.
Bus fabric aur single shared bus dono ek hi cheez ke do naam hain.
False — ek shared bus mein ek waqt mein bilkul ek hi transaction ho sakta hai (ek master wires ka malik hota hai). Ek fabric ek switching network hai jo multiple concurrent master→slave paths, har slave ke liye arbitration, aur QoS support karta hai.
AXI ke paanch channels ka matlab hai paanch alag physical buses hain jo paanch unrelated transactions run kar rahe hain.
False — paanch channels (AW, W, B, AR, R) read aur write ke directions/phases hain, paanch independent transaction streams nahi. Yeh ek transaction ke address, data, aur response phases ko overlap aur pipeline karne dete hain.
AXI mein master ko write address issue karne se pehle saara write data bhejna khatam karna zaroori hai.
False — Write Address (AW) aur Write Data (W) channels independent hain, isliye data address handshake se pehle, dauran, ya baad mein shuru ho sakta hai. Yahi decoupling alag channels rakhne ki poori wajah hai.
APB non-pipelined hai, isliye yeh AHB se strictly worse hai aur kabhi use nahi karna chahiye.
Intent mein False — APB ka minimal 2-cycle SETUP→ACCESS protocol deliberately simple hai low-speed peripherals (GPIO, timers, UART) ke liye jahan iska chota sa gate cost AHB ki unnecessary bandwidth se better hai.
Ek full crossbar ki cost ports ki number ke saath linearly badhti hai.
False — masters aur slaves ke liye crosspoint count hai, yeh ek product hai. Dono ko double karne se switches roughly quadruple ho jaate hain, isliye flat crossbars ~10–20 ports ke baad scale karna band kar dete hain.
AXI par zyada outstanding transactions add karne se hamesha effective throughput bina kisi limit ke badhti hai.
False — outstanding transactions latency tabhi hide karte hain jab tak slave ki actual bandwidth (ya buffer depth) saturate nahi hoti. Uske baad, zyada in-flight requests sirf queue karte hain; throughput slave ki physical limit par plateau ho jaata hai.
Arbitration sirf tab zaroori hai jab do masters alag-alag slaves ko target karein.
False — alag slaves ko bina kisi conflict ke parallel mein serve kiya ja sakta hai. Arbitration precisely tab zaroori hai jab do ya zyada masters ek hi slave ko target karein, isliye har slave port per ek arbiter zaroori hai.
Burst transfers isliye faster hote hain kyunki slave zyada clock par run karta hai.
False — ek burst kai data beats ke liye ek address handshake reuse karta hai, address overhead ko amortise karta hai. Clock unchanged rehti hai; faida yeh hai ki har byte ke liye kam address cycles lagte hain.

Error dhundo

"Humne ek shared bus use kiya, isliye CPU ka RAM read karna aur GPU ka peripheral read karna ek saath hota hai."
Error: ek shared bus saari traffic ko serialise karta hai — ek transaction mein sirf ek master bus ka malik hota hai. Yeh do accesses overlap nahi ho sakte; us parallelism ke liye tumhe ek multi-layer/crossbar fabric chahiye hoga.
"AXI write response (B channel) optional overhead hai jise hum channel bachane ke liye drop kar sakte hain."
Error: B response woh tarika hai jisse master ko pata chalta hai ki write actually commit hua ya nahi aur koi error toh nahi hai (BRESP). Ise drop karne ka matlab hai master completion kabhi confirm nahi kar sakta — faults par silent data loss hoga.
"4 masters aur 8 slaves ke liye humein 4 arbiters chahiye, ek per master."
Error: arbiters slaves par hote hain, masters par nahi, kyunki contention tab hoti hai jab kai masters ek slave ko hit karte hain. Tumhe arbiters chahiye, plus 8 address comparators, plus crosspoints.
"Ek firm IP core physical layout ke roop mein deliver hota hai, isliye yeh fully optimised hai."
Error: firm IP ek gate-level netlist ke roop mein ship hota hai, yeh ek middle ground hai jo abhi bhi kuch technology mapping allow karta hai. Physical-layout (GDSII) delivery ek hard core ki definition hai.
"APB throughput 32-bit, 100 MHz par 400 MB/s hai kyunki yeh har cycle mein 32 bits move karta hai."
Error: APB har transfer mein 2 cycles spend karta hai (SETUP + ACCESS), isliye yeh 32 bits per 2 cycles = 200 MB/s move karta hai. 400 MB/s figure AHB ki single-cycle pipelined rate hai.
"Kyunki AXI out-of-order completion support karta hai, read data hamesha address order mein wapas aata hai."
Error: out-of-order ka matlab hai responses issue hone ke alag order mein wapas aa sakte hain; transaction IDs tag karte hain ki kaunsa response kaunse request ka hai. Address order assume karna data mismatch karega.
"Ek DDR4 PHY ek soft IP core hai jise hum kisi bhi node ke liye synthesise kar sakte hain."
Error: ek DDR PHY mein analog/mixed-signal timing-critical circuitry hoti hai aur yeh ek hard core (fixed layout) ke roop mein ek process ke liye deliver hoti hai. Yeh synthesisable RTL nahi hai.

Why questions

AXI kyun har transfer ko AHB jaisi ek combined bus ki jagah alag address aur data channels mein split karta hai?
Kyunki address aur data phases ki timing aur lifetimes alag hoti hain; inhe alag karna slave ko address accept aur decode karne deta hai jabki master abhi data assemble kar raha hota hai, deep pipelining aur overlap enable hota hai.
Ek global arbiter poori fabric ke liye rakhne ki jagah ek arbiter per slave kyun rakha jaata hai?
Contention har shared resource ke liye local hoti hai — ek per-slave arbiter sirf unhi masters ke beech resolve karta hai jo uss slave ko aim kar rahe hain, baaki saare slave ports ko parallel mein proceed karne deta hai. Ek single global arbiter sab kuch unnecessarily serialise kar deta.
Hum ek 100-IP SoC ke liye ek giant flat crossbar kyun nahi bana sakte?
Cost crosspoints plus wiring congestion ke saath scale hoti hai, isliye ek 100-port crossbar area mein enormous aur unroutable hoga. Hierarchical fabrics / Network-on-Chip ise routers se jude chote local crossbars mein tod dete hain.
Ek burst transfer ko WLAST (last-beat) signal ki zaroorat kyun hoti hai?
Kyunki address phase ne sirf ek start aur length state kiya; slave ko abhi bhi final data beat par ek explicit marker chahiye yeh jaanne ke liye ki burst complete ho gaya aur transaction close karke apna response bheja ja sake.
Designers har block fresh design karne ki jagah verified IP cores kyun reuse karte hain?
Verification, design nahi, SoC schedules ko dominate karta hai; ek pre-verified core ko ek defined interface ke saath reuse karna development ko years se months tak cut karta hai aur team ko apni differentiating logic par focus karne deta hai.
AXI apne single-transaction number se suggest hone wale se zyada effective throughput kyun achieve karta hai?
Kyunki multiple transactions simultaneously in-flight ho sakte hain; jabki ek slave latency par wait kar raha hota hai, doosre progress karte hain, isliye latency hide hoti hai aur pipeline full rehti hai — jab tak slave ki raw bandwidth ise cap nahi karti.

Edge cases

Agar ek master ek aisa region address kare jo kisi bhi slave se map nahi hota toh crossbar par kya hoga?
Address decoder koi matching slave range nahi dhundh payega aur ek decode/error response return karna hoga (jaise AXI DECERR) rather than hang karna; bina kisi default error target ke ek fabric master ko response ka wait karte hue deadlock kar deti.
Do masters ek hi cycle mein ek hi slave ko request karte hain — kya toot-ta hai, aur kya bacha-ta hai?
Kuch nahi toot-ta agar slave ka arbiter ek winner pick kare aur doosre ko wait karaye; bina arbitration ke dono slave ko simultaneously drive karenge (bus contention / corruption). Arbiter ka poora kaam yahi hai.
Ek burst issue kiya gaya lekin master ka WVALID last beat ke liye kabhi assert nahi hota — kya state hai?
Transaction indefinitely stall ho jaata hai: slave ne address dekha hai lekin WLAST ke saath final data beat missing hai, isliye yeh complete nahi ho sakta ya B response issue nahi kar sakta. Yeh ek classic hang hai jise pending-outstanding count se debug karte hain.
Agar (single master) aur slaves hain, toh kya humein phir bhi arbiters chahiye?
Nahi — sirf ek master hone se koi bhi slave kabhi contended nahi ho sakta, isliye arbiters trivial pass-throughs mein collapse ho jaate hain. Tumhe abhi bhi sahi slave tak route karne ke liye address comparators chahiye.
Ek slave ke paas sirf ek buffer slot hai lekin ek master usse 4 outstanding reads issue karta hai — throughput ka kya hoga?
Slave sirf ek request hold kar sakta hai, isliye baaki teen master/fabric par queue karte hain aur kuch hासil nahi karte; effective throughput single-outstanding case tak drop ho jaata hai. Outstanding depth sirf slave ki buffering tak hi useful hai.
Ek shared bus ka throughput advantage over a crossbar kab appear hota hai?
Jab traffic genuinely low aur mostly serial ho (ek tiny microcontroller), shared bus area aur cost par jeetta hai — iska lack of parallelism irrelevant hai agar transactions kabhi overlap nahi karte, aur yeh crossbar ke hardware se bachata hai.
Recall Ek-line self-test

Arbitration kahan hota hai, aur wahan kyun? ::: Har slave port par, kyunki contention sirf tab hoti hai jab multiple masters ek hi slave ko target karein — ek per-slave referee baaki saare slaves ko parallel mein run karne deta hai.

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