Worked examples — DMA controllers

6.3.8 · D3 · Hardware › Interconnects, Buses & SoC › DMA controllers

Yeh page ek drill hall hai. Parent note ne machinery banayi thi — registers, state machine, transfer modes. Yahaan hum uss machinery ko use karte hain, aur deliberately awkward corner cases dhundhte hain: woh transfer jo poore words mein divide nahi hoti, zero-length request, woh moment jab CPU starve karta hai, aur fixed-width FIFO jo auto-increment nahi karni chahiye.

Har symbol jo hum use karte hain, usse pehli baar aane par re-anchor kiya gaya hai, taaki aap isse fresh padh sako.

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Scenario matrix

DMA transfer ko ek chhoti machine ki tarah socho jisme chaar dials hain: kitna data, kitna wide har step, kaun sa mode (kya yeh bus hog karti hai ya share karti hai?), aur kaunse addresses move karte hain (kya source/destination auto-increment karte hain, ya hardware FIFO pe pinned rehte hain?). Saare bugs aur exam traps un dials ke extremes pe rehte hain.

Cell	Case class	Tricky kyun hai	Kaun cover karta hai
A	Clean burst, sab kuch divide ho jaata hai	"Textbook" baseline	Ex 1
B	Byte count multiple of width nahi	Leftover partial word — round up? error?	Ex 2
C	Zero-length transfer (BCR = 0)	Degenerate: instantly finish hota hai ya hang?	Ex 3
D	Cycle-stealing vs burst usi job pe	Throughput vs CPU latency trade-off	Ex 4
E	Fixed source address (peripheral FIFO)	Increment bit 0 hona chahiye nahi to memory corrupt	Ex 5
F	Real-world word problem (SSD streaming)	Throughput requirement se mode choose karo	Ex 6
G	Transparent mode, CPU bus zyada use kar raha hai	Limiting behaviour: effective rate → bahut kam	Ex 7
H	Exam twist: do masters, priority scheme	Fixed vs round-robin mein starvation	Ex 8

Neeche ke aath examples har cell ko cover karte hain. Matrix ko apne dimag mein ek checklist ki tarah khula rakho.

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Recall Teen counters jo hum baar baar use karte hain

SAR = Source Address Register (yahaan se read karte hain). DAR = Destination Address Register (yahaan write karte hain). BCR = Byte Count Register (bytes abhi move karni hain — neeche count hoti hai). width = har step mein move hone wale bytes (1 = byte, 2 = halfword, 4 = word). Ek step karta hai: SAR pe read, DAR pe write, phir SAR += width (agar increment on ho), DAR += width (agar on ho), BCR -= width. Transfer tab khatam hoti hai jab BCR = 0. Dekho Memory-Mapped IO taaki samjho CPU in registers ko kaise poke karta hai.

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Cell A — clean baseline

1. Transfers count karo. $N=\frac{\text{BCR}}{\text{width}}=\frac{4096}{4}=1024$. Yeh step kyun? Har step width = 4 bytes move karta hai, isliye steps ki sankhya total bytes ÷ 4 hai. Yeh 4096 se kam hai — wider steps matlab unki sankhya kam.
2. Setup + per-transfer cycles add karo. Parent se burst time model: $T_{\text{burst}}=T_{\text{setup}}+N\times T_{\text{cycle}}=4+1024\times 1=1028\text{ cycles}.$ Yeh step kyun? Burst mode mein DMA bus ko ek baar pakadta hai (setup ek baar pay karo) phir saare 1024 transfers back-to-back fire karta hai — setup cost amortise ho jaati hai.
3. Cycles → time convert karo. 100 MHz pe ek cycle $\frac{1}{100\times 10^6}\text{s}=10\text{ ns}$ hai. $T_{\text{burst}}=1028\times 10\text{ ns}=10280\text{ ns}=10.28\mu \text{s}.$ Yeh step kyun? Bus clock ek cycle ki length set karta hai; frequency aur period reciprocals hain.

Verify: $1024\times 4=4096$ bytes ✓ (saara data account ho gaya). CPU poori 10.28 μs blocked rehta hai kyunki burst mode transfer ke beech mein bus kabhi release nahi karta.

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Cell B — byte count jo divide nahi hota

Forecast: memory-to-memory copy ke liye padhne se pehle decide karo kaun sa safer hai.

1. Integer division karo. $\lfloor 4098/4\rfloor =1024$ full 32-bit transfers = 4096 bytes. Yeh step kyun? Floor, round nahi — aap requested bytes se zyada kabhi move nahi kar sakte.
2. Remainder calculate karo. $4098-4096=2$ bytes bache. Yeh step kyun? Yahi woh tail hai jo full-word engine reach nahi kar sakta.
3. Fix-up transfer emit karo. Ek well-designed controller ek final step ke liye width ko 2 (halfword) par drop karta hai: 1 halfword = 2 bytes → BCR exactly 0 ho jaata hai. Yeh step kyun? Ek narrower final beat exact byte boundary pe land karta hai bina agle memory location ko over-write kiye.
4. Total transfers = 1024 (word) + 1 (halfword) = 1025 beats.

Verify: $1024\times 4+1\times 2=4096+2=4098$ ✓. Agar controller mein remainder support nahi hai, toh sahi behaviour error out karna hai — kabhi silently 4100 bytes mat likho (yeh buffer ke baad 2 bytes clobber karega, ek classic overflow bug).

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Cell C — degenerate zero-length transfer

Forecast: bahut se students kehte hain "yeh ek transfer karta hai." Ordering dekho.

1. FSM exit test dobara padho. Parent ki machine BCR = 0 check karti hai transfer ke baad, lekin ek sahi design isme transfer state mein entry pe bhi check karta hai. Yeh step kyun? Agar aap sirf baad mein test karo, toh zero-length job notice karne se pehle ek unwanted transfer karega — ek aisa byte move karega jo aapne kabhi maanga nahi tha.
2. Entry guard turant fire karta hai. BCR pehle se 0 hone par, State 2 (TRANSFER) bilkul skip ho jaata hai; machine IDLE → REQUEST → check → DONE jump karti hai. Yeh step kyun? Zero kaam maanga = zero kaam hua.
3. Done bit + interrupt phir bhi fire karte hain. Yeh CSR.Done = 1 set karta hai aur IRQ raise karta hai agar IE = 1 ho. Yeh step kyun? Software jo completion ka wait kar raha ho use wake up karna zaroori hai chahe transfer empty ho, warna deadlock ho jaata hai.

Verify: transfers executed = $\max (0,\lfloor 0/4\rfloor )=0$ ✓. Bytes written = 0 ✓. Machine terminate karti hai (hang nahi karti), yahi entry guard ka poora point hai.

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Cell D — same job, do modes

Forecast: slowdown factor guess karo — 2×? 4×?

1. Cycle-steal time model. DMA bus ko har beat pe grab aur release karta hai, isliye setup har transfer pe pay hoti hai: $T_{\text{cs}}=N\times (T_{\text{arb}}+T_{\text{transfer}})=1024\times (3+1)=4096\text{ cycles}.$ Yeh step kyun? Koi amortisation nahi — har beat re-arbitrate karta hai. Woh $+3$ politeness ki qeemat hai.
2. Convert karo. $4096\times 10\text{ ns}=40960\text{ ns}=40.96\mu \text{s}$.
3. Slowdown factor. $\frac{40.96}{10.28}=3.98\approx 4\times$ burst se slower. Yeh step kyun? Har beat ab 1 ki jagah 4 cycles leta hai — isliye ~4×.
4. Lekin: har beat ke beech CPU bus seize kar sakta hai. Worst-case CPU wait 1028 cycles (poori burst) se ghata ke lagbhag 4 cycles (ek beat) ho jaata hai. Yeh step kyun? Cycle-stealing throughput ko latency ke liye trade karta hai — tab zaroori jab CPU ke real-time deadlines hon.

Verify: $1024\times (3+1)=4096$ ✓ aur $4096/1028=3.984$ ✓. Throughput mein burst jeetta hai; CPU responsiveness mein cycle-stealing. Dekho Bus Architecture taaki samjho request/grant lines yeh hand-off kaise possible banate hain.

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Cell E — fixed address (peripheral FIFO)

Forecast: padhne se pehle decide karo kaun sa increment bit 0 hoga aur kaun sa 1?

1. Source ek FIFO hai → SAR fix karo. Set karo CSR bit 6 (Increment SAR) = 0. SAR saare 16 reads ke liye 0x4000_1000 pe rehta hai. Yeh step kyun? Hardware same address se har read pe ek naya byte present karta hai; address move karne se galat registers read honge.
2. Destination ek buffer hai → DAR increment karo. Set karo CSR bit 7 (Increment DAR) = 1. DAR 0x2000_0000, 0x2000_0001, … walk karta hai. Yeh step kyun? Har captured byte ko apna memory slot chahiye; RAM addresses aage badhne chahiye.
3. BCR = 16, width = 1 → $N=16/1=16$ beats.

Verify (last few beats ka trace):

Beat	read from (SAR)	write to (DAR)	BCR after
1	0x40001000	0x20000000	15
2	0x40001000	0x20000001	14
…	0x40001000	…	…
16	0x40001000	0x2000000F	0

Final DAR = 0x2000_0000 + 15 = 0x2000_000F, BCR = 0 ✓. SAR kabhi nahi hila ✓.

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Cell F — real-world word problem

Forecast: required utilisation percentage mein guess karo — 100% se kam?

1. Peak DMA bandwidth. Bytes/beat × beats/sec: $B_{\max }=8\text{ bytes}\times 200\times 10^6\text{beat/s}=1.6\times 10^9\text{B/s}=1.6\text{GB/s}.$ Yeh step kyun? Bandwidth = (data per event) × (events per second). Yeh ceiling hai agar DMA bus 100% own kare.
2. Demand se compare karo. Demand = 2.0 GB/s. Kyunki $1.6<2.0$, ek single 64-bit/200 MHz channel full utilisation pe bhi keep up nahi kar sakta. Yeh step kyun? Required utilisation $=2.0/1.6=1.25=125\%$ — impossible, bus ko 100% se zyada use nahi kar sakte.
3. Fix options. 128-bit tak widen karo ($B_{\max }=3.2$ GB/s → chahiye $2.0/3.2=62.5\%$) ya clock 250 MHz tak badhao ($8\times 250\text{M}=2.0$ GB/s → exactly 100% chahiye, koi margin nahi). Yeh step kyun? Bandwidth width aur clock dono ke saath scale karta hai; koi bhi ek badhao ke headroom milta hai.

Verify: $8\times 200\text{e}6=1.6\text{e}9$ ✓; $2.0/1.6=1.25$ ✓; widened $8\times 2\times 200\text{e}6=3.2\text{e}9$ aur $2.0/3.2=0.625$ ✓. 37.5% safety margin ke liye 128-bit choose karo — real systems shared bus ko 100% pe nahi chalate.

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Cell G — transparent mode, limiting behaviour

Forecast: agar CPU 90% hog kare, toh roughly kitna fraction DMA ke liye bachega?

1. Free-cycle fraction. CPU 90% busy ⇒ DMA sirf $1-0.90=0.10=10\%$ cycles dekhta hai. Yeh step kyun? Transparent DMA ek scavenger hai — yeh bache-khuche pe jeeta hai, kabhi compete nahi karta.
2. Effective beats/sec. $0.10\times 100\times 10^6=10\times 10^6$ beats/s.
3. Effective bandwidth. $10\times 10^6\text{beat/s}\times 4\text{B/beat}=40\times 10^6\text{B/s}=40\text{MB/s}$. Yeh step kyun? Same bandwidth formula, free fraction se throttle.
4. Limiting case. Jab CPU usage → 100%, free fraction → 0, isliye effective rate → 0 B/s. Transfer kabhi khatam nahi hogi. Yeh step kyun? Yahi transparent mode ki fatal flaw hai: zero CPU interference, lekin throughput unpredictable ho jaati hai aur zero tak collapse kar sakti hai.

Verify: $0.10\times 100\text{e}6\times 4=4.0\text{e}7=40$ MB/s ✓; ${\lim }_{u\to 1}(1-u)\cdot R=0$ ✓. Burst mode ke guaranteed 400 MB/s (100% × 100M × 4) se compare karo — transparent mode us guarantee ko zero CPU stall ke badle trade karta hai.

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Cell H — exam twist: do masters, priority

Forecast: kaun sa scheme kisi ko starve karta hai, aur kaun sa "fair but dono ke liye slow" hai?

1. Feasibility check karo. $60\%+60\%=120\%>100\%$ — bus oversubscribed hai, kisi ko lose karna hoga. Yeh step kyun? Aap ek shared resource ka 100% se zyada allocate nahi kar sakte; sirf sawaal yeh hai ki shortfall kaise distribute hota hai.
2. Fixed priority. Disk arbitration mein hamesha jeetta hai ⇒ Disk ko apna poora 60% milta hai. Net ko jo bachta hai milta hai: $100\%-60\%=40\%$. Net starved hai apni 60% need se neeche (sirf 40% deliver). Yeh step kyun? Daisy-chained fixed priority (parent note) kabhi lower device ko higher wale ko pre-empt nahi karne deta — simple hardware, unfair outcome.
3. Round-robin. Bus grants alternate karta hai, isliye har channel ko 100% ka equal share milta hai: $50\%$ each. Yeh step kyun? Rotating priority (parent ka $(i+1)\mathrm{mod}N$ rule) access equalise karta hai — dono 60% se short hain, lekin equally short.
4. Shortfalls compare karo. Fixed: Net $60-40=20$ points miss karta hai, Disk theek. Round-robin: dono $60-50=10$ points miss karte hain. Yeh step kyun? Fairness pain spread karti hai; worst-case channel better off rehta hai (10 vs 20 points short).

Verify: fixed $\Rightarrow 60+40=100$ ✓ (Net 20 se starved); round-robin $\Rightarrow 50+50=100$ ✓ (dono 10 se short). Dekho Bus Architecture aur parent ka arbitration section. Jab dono devices real-time hon, round-robin ki bounded fairness isliye prefer ki jaati hai.

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Recall checkpoint

Recall

4098-byte transfer at 32-bit width mein kitne beats lagte hain (remainder support ke saath)? ::: 1025 — 1024 word beats (4096 B) plus ek halfword beat (2 B). FSM BCR=0 entry pe kyun test karta hai, sirf transfer ke baad nahi? ::: Taaki zero-length request zero bytes move kare, na ki notice karne se pehle ek unwanted byte. Fixed peripheral FIFO padhne ke liye, kaun sa increment bit 0 hai? ::: Increment SAR (bit 6) = 0 — FIFO address pinned rehna chahiye; sirf DAR aage badhta hai. Cycle-stealing yahaan ~4× burst se slow tha. 4× kahan se aaya? ::: Har beat 3 arbitration + 1 transfer = 4 cycles pay karta hai, burst ke 1 amortised cycle ki jagah. 64-bit / 200 MHz bus ki peak bandwidth kya hai? ::: 8 B × 200e6 = 1.6 GB/s — ek 2.0 GB/s SSD se kam, isliye widen ya clock up karna padega. Transparent mode mein, CPU bus usage → 100% hone par DMA rate kya hogi? ::: Yeh → 0 B/s ho jaati hai; DMA bilkul starve ho jaata hai.

Related depth: Cache Coherency (kyun DMA writes cache mein stale ho sakti hain), SDRAM Controllers (in beats ka memory side), ARM AMBA AXI (ek real bus jo yeh arbitration implement karta hai).