Visual walkthrough — DMA controllers

6.3.8 · D2 · Hardware › Interconnects, Buses & SoC › DMA controllers

Ye page ek bahut concrete sawaal ka jawaab deti hai, bilkul zero se:

Jab ek DMA controller $N$ chunks of data move karta hai, toh kitna time lagta hai — aur us time mein se kitna CPU se chura liya jaata hai?

Parent note (DMA controllers) ne tumhe burst aur cycle-stealing modes ke liye do headline formulas diye the. Yahaan hum un formulas ko ek blank timeline se build karte hain, ek clock tick at a time, taaki tum dekh sako ke har number kahan se aata hai.

Hum kuch bhi assume nahi karte. Agar tumne kabhi "bus", "clock cycle", ya symbol $N$ nahi dekha, toh end tak dekh loge.

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Step 1 — "Clock cycle" kya hota hai, aur hum time kyun unhi mein measure karte hain

KYA HAI. Ek digital chip mein ek clock hota hai: ek signal jo up-down-up-down hamesha tick karta rehta hai, jaise ek metronome. Ek poori tick ko clock cycle kehte hain. Hardware jo bhi karta hai — ek byte padhna, address mein add karna — yeh sab inhi ticks par hota hai.

KYUN. Hum hardware time ko directly seconds mein measure nahi kar sakte, kyunki wahi design alag-alag speeds par run ho sakti hai. Isliye hum cycles count karte hain (ek pure count, koi units nahi), phir end mein clock ki frequency use karke seconds mein convert karte hain. Yeh "kitne steps" aur "har step kitna fast hai" ko alag rakhta hai.

PICTURE. Neeche, har chhota box ek cycle hai. Clock frequency $f$ (ticks per second) batati hai ki ek single cycle seconds mein kitni der ka hota hai. Us duration ko $t_{\text{sec}}$ kaho:

$\underset{\text{seconds in ONE cycle}}{\underbrace{t_{\text{sec}}}}=\frac{1}{\underset{\text{ticks per second}}{\underbrace{f}}}$

Toh $f=100\text{ MHz}=100,000,000$ ticks/second par, ek cycle $t_{\text{sec}}=\frac{1}{100000000}\text{s}=10\text{ns}$ ka hota hai.

Do alag cheezein hain, inhe confuse mat karo: $t_{\text{sec}}$ hai seconds per one cycle (ek conversion factor, units: seconds). Baad mein, $T_{\text{cycle}}$ hoga kitne cycles ek data transfer mein lagte hain (ek count, units: cycles). Real time paane ke liye hum multiply karte hain: $\text{(cycle count)}\times t_{\text{sec}}=\text{seconds}$.

Prerequisite plumbing Bus Architecture mein hai — woh shared wires jis par data travel karta hai.

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Step 2 — DMA actually kya move kar raha hai: fixed width ke $N$ transfers

KYA HAI. Move kiya jaane wala data bytes ka ek block hota hai — maan lo $B$ bytes total. Lekin bus ek time mein ek byte nahi move karti; woh ek baar mein fixed width $w$ bytes move karti hai (1, 2, ya 4 bytes, control register ke width bits se choose hota hai). Har width-sized gulp ko one transfer kehte hain.

KYUN. Ek 32-bit-wide bus 4 bytes ek hi single cycle mein carry karti hai jisme woh 1 byte carry karti — wires toh already wahan hain. Toh hum transfers count karte hain, bytes nahi. Transfers ki sankhya hai:

$N=\frac{\stackrel{\text{total bytes}}{\overbrace{B}}}{\underset{\text{bytes per transfer}}{\underbrace{w}}}$

PICTURE. Ek $B=4096$-byte block ko $w=4$-byte pieces mein kaatne se $N=1024$ pieces milte hain. Har piece bus ke paas ek trip hai.

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Step 3 — EK transfer ki cost: read, phir write

KYA HAI. Ek memory-to-memory DMA transfer actually do bus actions hain: source ko read karo, destination mein write karo. Ek back-to-back optimized bus par yeh pipeline full hone ke baad roughly ek bus cycle ke steady-state throughput mein overlap ho jaate hain. Hum is steady per-transfer time ko $T_{\text{cycle}}$ kehte hain — un cycles ki sankhya jo ek already-warmed-up transfer consume karta hai.

KYUN. Humein ek honest number chahiye ki "jab machine ek gulp of data par warmed up ho jaaye toh kitna time lagta hai?" Baaki sab overhead is par layered hai. Ise isolate karne se hum do modes ke baare mein alag-alag reason kar sakte hain.

PICTURE. Read source address (Memory-Mapped IO-style) ko wires par dalta hai, data grab karta hai; write destination address dalta hai aur data bahar push karta hai. Steady-state mein, har naya transfer har $T_{\text{cycle}}\approx 1$ cycle mein complete hota hai.

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Step 4 — Woh overhead jo DMA skip nahi kar sakta: arbitration

KYA HAI. DMA controller bus ka malik nahi hai. Use karne ke liye, use poochhna padta hai: woh ek "bus request" wire assert karta hai aur arbiter ke "grant" ke saath jawaab ka intezaar karta hai. Yeh request→grant handshake kuch cycles costa hai aur koi data movement nahi karta. Ise $T_{\text{arb}}$ (arbitration) kaho.

$T_{\text{arb}}$ aur $T_{\text{setup}}$ ka aapas mein sambandh: Burst mode mein hum ek bade startup block ke liye pay karte hain jise $T_{\text{setup}}$ kehte hain, jo ki arbitration plus bus par pehla address dalna hai: roughly $T_{\text{setup}}=T_{\text{arb}}+(\text{first-address setup})$. Toh $T_{\text{setup}}$ $T_{\text{arb}}$ se thoda bada hota hai (hamare example mein $T_{\text{setup}}=4$ cycles versus $T_{\text{arb}}=3$ cycles). Key point: $T_{\text{setup}}$ ek baar pay kiya jaata hai, jabki $T_{\text{arb}}$ har transfer ke liye pay kiya jaata hai.

KYUN. Bus CPU aur har DMA channel ke beech shared hai (dekho ARM AMBA AXI arbiters). Kisi ko decide karna padta hai ki har cycle mein kaun wires drive karta hai, warna do devices ladte aur data corrupt ho jaata. Yeh decision free nahi hai.

PICTURE. Grey "waste" cycles arbitration hain; coloured cycles real data hain. Transfer mode choose karne ka poora game hai: hum yeh grey tax kitni baar pay karte hain?

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Step 5 — Burst mode: tax EK BAAR pay karo

KYA HAI. Burst mode mein DMA bus ke liye ek baar maangta hai, phir use pakad kar saare $N$ transfers back-to-back fire karta hai release karne se pehle. Total time (cycles mein):

$T_{\text{burst}}=\underset{\text{arb + first address, paid once}}{\underbrace{T_{\text{setup}}}}+\underset{\text{transfers}}{\underbrace{N}}\times \underset{\text{cycles per transfer}}{\underbrace{T_{\text{cycle}}}}$

KYUN. Kyunki hum sirf ek baar maangte hain, setup cost amortized hai — saare $N$ transfers mein phaili hui. Yeh sabse fast possible mode hai: pure data movement ek single chhoti si prefix ke saath.

PICTURE. Shuru mein ek chhota grey block, phir data cycles ki ek lambi unbroken rainbow.

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Step 6 — Cycle-stealing mode: tax HAR BAAR pay karo

KYA HAI. Cycle-stealing mode mein DMA maangta hai, ek transfer karta hai, bus release karta hai, phir agle ke liye dobara maangta hai. $N$ transfers mein se har ek ab apna arbitration cost $T_{\text{arb}}$ aur wahi per-transfer data cost $T_{\text{cycle}}$ (jo humne Step 3 mein define ki thi) carry karta hai:

$T_{\text{cycle-steal}}=N\times (\underset{\text{ask, paid every time}}{\underbrace{T_{\text{arb}}}}+\underset{\text{one gulp of data (same symbol as Step 3)}}{\underbrace{T_{\text{cycle}}}})$

KYUN. Transfers ke beech bus release karke, DMA CPU ko beech mein aane aur responsive rehne deta hai (Interrupts-driven kaam stall nahi hota). Iska price yeh hai ki grey tax ab amortized nahi hai — woh $N$ se multiply ho jaata hai.

PICTURE. Grey-colour-grey-colour, hamesha ke liye alternating. CPU gaps mein ek turn le sakta hai.

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Step 7 — Edge aur degenerate cases (koi gap mat chhodo)

KYA HAI. Do formulas ko unke extremes par stress-test karte hain. Pehle ek naam: Byte Count Register (BCR) DMA ke andar woh hardware counter hai jo hold karta hai ki kitne bytes abhi move karne hain; controller har transfer ke baad ise decrement karta hai aur zero hone par ruk jaata hai. Toh "$N=0$" matlab "BCR zero se start hua — kuch queue nahi".

CASE $N=0$ (move karne ke liye kuch nahi). BCR $0$ se start hota hai.

• Burst: formula deta hai $T=T_{\text{setup}}+0\times T_{\text{cycle}}=T_{\text{setup}}$. Lekin ek real controller $\text{BCR}=0$ inspect karta hai arbitrate karne ki koshish se pehle, aur seedha "done" par short-circuit karta hai, toh practically $T=0$. Formula aur optimization tab agree karte hain jab tum formula ko "cost given that we entered the transfer state machine" ke roop mein padho; BCR=0 pre-check simply matlab hai hum kabhi enter nahi karte, toh $T_{\text{setup}}$ kabhi spend nahi hota. Koi contradiction nahi — formula describe karta hai kaam jo hua, pre-check avoid karta hai koi kaam karna.
• Cycle-steal: $T=0\times (T_{\text{arb}}+T_{\text{cycle}})=0$. Consistent — koi transfers nahi, koi cost nahi.

CASE $N=1$ (ek single transfer). Do modes converge karte hain: $T_{\text{burst}}=T_{\text{setup}}+T_{\text{cycle}},T_{\text{cycle-steal}}=T_{\text{arb}}+T_{\text{cycle}}$ $T_{\text{setup}}\approx T_{\text{arb}}$ ke saath, burst ka amortization advantage gayab ho jaata hai — ek item par ek baar ka cost spread nahi ho sakta.

CASE $N\to \infty$ (bahut bada transfer). Setup term $N$ ke against negligible ho jaata hai: $\frac{T_{\text{burst}}}{N}\stackrel{N\to \infty }{\to }{T}_{\text{cycle}},\frac{T_{\text{cycle-steal}}}{N}\stackrel{N\to \infty }{\to }{T}_{\text{arb}}+T_{\text{cycle}}$ Toh bade blocks ke liye per-transfer cost — timeline ka slope — hi sab kuch matter karta hai, aur burst fixed ratio $\frac{T_{\text{arb}}+T_{\text{cycle}}}{T_{\text{cycle}}}$ se jeet jaata hai.

PICTURE. Do lines: time versus $N$. Dono straight hain; woh $N=1$ ke paas cross karte hain aur fan apart hote hain. Slope per-transfer cost hai; y-intercept setup tax hai.

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Ek-picture summary

Upar sab kuch ek single timeline comparison mein collapse hota hai: wahi $N$ transfers, do baar draw kiye gaye — burst (ek tax, phir ek clean run) versus cycle-stealing (har gulp se pehle ek tax). Grey ka area wasted time hai; coloured area dono mein identical hai.

$\boxed{T_{\text{burst}}=T_{\text{setup}}+N{T}_{\text{cycle}}{T}_{\text{cycle-steal}}=N(T_{\text{arb}}+T_{\text{cycle}})}$

Recall Feynman retelling — ek dost ko explain karo

DMA ek courier hai jo $N$ parcels ek shared hallway (bus) ke paas le jaata hai. Hallway mein jaane se pehle use guard se permission maangni padti hai — yeh "maangna" kuch seconds waste karta hai aur koi parcels move nahi karta.

Burst mode mein courier ek baar maangta hai, phir bina ruke saare $N$ parcels sprint karke le jaata hai. Maangne ki cost ($T_{\text{setup}}$) sirf ek baar pay hoti hai, toh bahut parcels ke saath yeh basically free per parcel ho jaati hai. Lekin jab tak courier daudta rehta hai poora hallway block rehta hai — koi aur (CPU) nahi nikal sakta.

Cycle-stealing mode mein courier polite hai: maango, ek parcel le jaao, chale jao, phir maango, agla le jaao. CPU trips ke beech slip kar sakta hai, toh sab responsive rehte hain — lekin ab "maangna" ($T_{\text{arb}}$) $N$ baar hota hai, aur hamare example numbers ke liye yeh approximately chaar guna zyada time add karta hai.

Math bas yahi hai: time = (ek baar ka maangna) + (parcels ki sankhya × time per parcel) burst ke liye, versus (parcels ki sankhya × (maangna + le jaana)) cycle-stealing ke liye, jahan "ek parcel le jaana" dono mein wahi $T_{\text{cycle}}$ hai. Jab zero parcels hon (BCR 0 se start hua), dono kuch nahi cost karte. Jab ek parcel ho, dono same hain. Jab hazaaron hon, slope (per-parcel cost) hi sab kuch hai, aur burst ka shallower slope jeet jaata hai — hallway block karne ki keemat par. Poora engineering choice yahi hai: guard ko kitni baar pay karte ho?

Related coherence concerns jab DMA woh memory likhta hai jo CPU ne cache ki hai: dekho Cache Coherency.