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6.3.8 · D5 · HinglishInterconnects, Buses & SoC

Question bank — DMA controllers

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6.3.8 · D5 · Hardware › Interconnects, Buses & SoC › DMA controllers

Yeh page aapke DMA controllers ke mental model ka stress-test hai. Neeche har item ek specific misconception ya boundary case ko target karta hai. Answer cover karo, pehle ek reason commit karo (sirf haan/naa nahi), phir reveal karo.

Questions se pehle, ek ek-line refresher un vocabulary par jo hum baar baar use karenge. Agar inme se koi bhi fuzzy lage, pehle parent note dobara padho.

Recall Vocabulary jo aapko ready rakhni chahiye
  • SAR / DAR / BCR ::: Source Address, Destination Address, aur Byte Count registers — kahan se padhna hai, kahan likhna hai, kitna bacha hai.
  • Bus master ::: ek device jo address/data bus ko khud drive kar sakta hai, sirf respond nahi. DMA controller ek hai; CPU bhi ek hai.
  • Cycle stealing ::: DMA ek transfer ke liye bus pakad ta hai, release karta hai, aur agle ke liye phir se maangta hai.
  • Burst mode ::: DMA ek baar bus pakadta hai aur poore block ke liye hold karta hai.

True ya false — justify karo

Answer cover karo. True/false aur kyun bolo.

DMA ek peripheral ko data transfer karne deta hai zero CPU involvement ke saath.
False — CPU per byte involve nahi hota, lekin transfer shuru karne ke liye woh SAR/DAR/BCR/CSR program karta hai aur usually end mein completion interrupt service karta hai. Yeh "beech mein hands-off" hai, "poori tarah hands-off" nahi.
Burst mode hamesha cycle stealing se transfer zyada fast karta hai.
True DMA transfer ke apne wall-clock time ke liye, kyunki yeh arbitration overhead ek baar pay karta hai instead of har transfer par — lekin yeh poore system ko slow karta hai CPU ko lock out karke, isliye "faster" sirf us block ke isolation mein hold karta hai.
Jab DMA burst mode mein bus hold karta hai, CPU completely frozen hota hai.
Mostly false — CPU koi bhi kaam jo apne andar hi rehta hai woh chala sakta hai (register ALU ops, cache hits). Woh sirf tab stall karta hai jab use external bus chahiye aur woh DMA ko granted mila ho.
DMA controller ek tarah ka CPU hai.
False — iske paas koi instruction fetch/decode nahi hai aur yeh koi program nahi chalata. Yeh ek fixed finite-state machine hai jo apne registers se driven hota hai; yeh sirf bytes move kar sakta hai, decisions nahi le sakta ya data par branch nahi kar sakta.
Transparent mode teeno modes mein sabse zyada guaranteed throughput deta hai.
False — yeh sabse kam CPU disturbance deta hai lekin sabse kharab aur least predictable throughput, kyunki yeh sirf un gaps mein transfer karta hai jab CPU bus use nahi kar raha. Ek bus-hungry CPU ise starve kar sakta hai.
Memory-to-memory (M2M) copies abhi bhi DMA se benefit karti hain chahe koi peripheral involve na ho.
True — faida yeh hai ki CPU per-byte load/store loop se free ho jaata hai; source aur destination dono RAM hona yeh nahi badalti ki CPU otherwise lakhon instructions burn karta (Memory-Mapped IO ke alawa, yeh pure data shuffling hai).
EN bit set karna hi transfer shuru karta hai, toh baaki registers likhne ka order matter nahi karta.
True is sense mein ki SAR/DAR/BCR/CSR-mode bits sirf latched values hain jinka EN tak koi side effect nahi — lekin aapko EN se pehle inhe likhna zaroor khatam karna chahiye, warna state machine stale/garbage addresses ke saath launch ho jaayegi.
Fixed-priority arbitration mein koi device kabhi bhi forever wait nahi kar sakta.
False — yahi iska weakness hai. Ek high-priority master jo continuously request karta hai har lower-priority device ko indefinitely starve kar sakta hai; rotating priority isi ko rokne ke liye exist karta hai.
Done bit aur interrupt line same information carry karte hain, toh dono hona redundant hai.
False — Done bit ek pulled status hai jo aap poll karte ho; interrupt ek pushed asynchronous signal hai. Done bit chahiye taaki ek handler completion confirm kar sake, aur interrupt (Interrupts ke through) busy-polling se bachne ke liye. Yeh complement karte hain, duplicate nahi.

Error dhundho

Har statement mein ek galti hai. Use name karo aur correct version do.

"32-bit-wide transfer ke liye, DMA har transfer ke baad SAR ko 1 se increment karta hai."
Wrong step size — ek 32-bit (word) transfer 4 bytes move karta hai, toh SAR 4 se increment hota hai, 1 se nahi. Increment transfer width ke barabar bytes mein hoti hai, isliye width field address arithmetic ko control karta hai.
"BCR 0 se upar count karta hai jab tak yeh transfer size tak nahi pahunchta, phir ruk jaata hai."
Ulta hai — BCR byte count ke saath load hota hai aur neeche count karta hai; ek hardware comparator termination trigger karta hai jab BCR 0 tak pahunchta hai. Neeche count karna matlab terminate condition ek simple "== 0" check hai.
"Ek peripheral ke saath 1 KB copy karne ke liye, Direction = M2M set karo."
Wrong direction code — ek peripheral involve hai, toh yeh P2M (peripheral-to-memory) ya M2P hai, M2M nahi. M2M ka matlab hai dono endpoints ordinary memory addresses hain.
"Cycle stealing burst se zyada fast hai kyunki ise bus ka wait nahi karna padta."
Bilkul ulta hai — cycle stealing har single transfer par bus ke liye re-arbitrate karta hai, har baar add karta hai, toh yeh per block slower hai. Iska advantage CPU responsiveness hai, speed nahi.
"DMA finish hone ke baad, CPU immediately data trust kar sakta hai kyunki transfer CPU ke cache se gaya."
Galat — DMA typically seedha memory mein likhta hai, CPU cache ko bypass karke. CPU ke paas abhi bhi stale cached copies ho sakti hain, toh handler ko cache invalidate/flush karna padega. Yahi Cache Coherency problem hai jo DMA create karta hai.
"256-transfer maximum burst length field (bits 8–15) ke saath, aap per burst sirf 256 bytes transfer kar sakte ho."
Transfers aur bytes ko confuse kar raha hai — 256 transfers at, say, word width hai 256 × 4 = 1024 bytes. Burst length transactions count karta hai, aur har transaction width bytes move karta hai.

Why questions

Reason do, sirf fact nahi.

DMA controller ko bus request/grant handshake ki zaroorat kyun hai?
Kyunki woh aur CPU dono bus masters hain jo same shared wires chahte hain. Ek waqt mein sirf ek hi address/data bus drive kar sakta hai, toh ek arbiter ko DMA ke kuch bhi drive karne se pehle exclusive ownership grant karni chahiye — warna do drivers ladte hain aur bus corrupt ho jaata hai.
Burst mode "unfair" kyun hai chahe efficient ho?
Kyunki yeh bus ko poore block ke liye hold karta hai, toh har doosra master — CPU, doosre DMA channels — poori duration ke liye locked out rehta hai. Ek transfer ke liye efficiency baki sabke liye starvation ban jaati hai.
Transparent mode CPU ke liye zero extra latency cost ke saath transfers kaise achieve kar sakta hai?
Kyunki yeh sirf un cycles mein data move karta hai jab CPU waise bhi external bus use nahi karne wala tha (cache hits, internal ops). Yeh idle bus slots fill karta hai, toh CPU kabhi notice nahi karta ki bus "busy" hai.
Har DMA register CPU dwara writable aur DMA logic dwara readable/writable kyun hona chahiye?
CPU unhe ek baar transfer set up karne ke liye likhta hai; DMA logic phir SAR/DAR padhta hai bus drive karne ke liye aur unhe wापas likhta hai har step par increment/decrement karke. Dono sides same registers ko alag phases mein touch karte hain.
SSDs (3+ GB/s) jaise fast devices DMA ko sirf nice-to-have ki jagah essential kyun banate hain?
DMA ke bina CPU apne 100% cycles us rate par sirf load/store copy loop execute karne mein spend karta, actual programs ke liye kuch nahi bachta. DMA byte-shuffling ko instruction stream se hata deta hai taaki CPU real kaam concurrently kar sake.
Transfer-width field ek saath bus transaction size aur address increment kyun control karta hai?
Kyunki woh same physical quantity hain — ek word transfer bus par 4 bytes move karta hai aur address pointer ko 4 se advance karta hai. Inhe decouple karna controller ko bytes skip ya overlap karne deta, jo ek linear copy ke liye nonsensical hai.
Done bit CPU ki side se read-only kyun rakhte hain?
Kyunki Done hardware state reflect karta hai (BCR zero hit hua). Agar CPU ise arbitrarily likh sakta, software falsely claim kar sakta ki transfer finish ho gayi — yeh status us state machine ki honi chahiye jo actually jaanta hai.

Edge cases

Woh boundaries jahan naive models toot jaate hain.

Kya hota hai agar CPU EN set kare jabki BCR already 0 ho?
Comparator immediately BCR = 0 dekha hai, toh state machine seedha DONE mein ja sakti hai bina koi byte move kiye — ek zero-length transfer. Achhe designs ise ek completed no-op treat karte hain (aur completion interrupt bhi raise kar sakte hain agar IE = 1 ho).
Agar M2M copy mein source aur destination regions overlap karein toh kya hoga?
DMA ek seedha incrementing copy karta hai bina kisi overlap detection ke, toh naive memcpy ki tarah yeh data corrupt kar sakta hai jab destination source se aage overlap kare. Overlap-safe moves caller ki responsibility hain; hardware aapko protect nahi karega.
Cycle-stealing mode mein ek bahut bus-busy CPU ke saath, DMA throughput kya limit karta hai?
Woh rate jis par DMA CPU cycles ke beech arbitration jeet sakta hai. Agar CPU bus rarely yield karta hai, DMA ke grants slowly aate hain, toh throughput transfer ki raw capability se kaafi neeche gir jaata hai — wohi starvation jo transparent mode face karta hai, lekin yahan arbitration overhead explicit hai.
Agar "increment SAR" bit 0 ho (fixed address) toh kya hota hai?
SAR har transfer par ek hi address par pinned rehta hai — yeh ek peripheral FIFO ke liye sahi hai jahan aap hamesha same data register se padhte ho (dekho UART ya ek SDRAM data port). Wahan increment karna unrelated registers mein walk off kar deta.
Agar ek higher-priority master transfer ke beech mein bus request kare toh in-flight burst ka kya hoga?
Pure burst mode mein, kuch nahi — burst non-preemptible hai aur requester block complete hone tak wait karta hai. Yahi reason hai ki long bursts latency hurt karte hain; jo systems bounded latency chahte hain woh ya toh burst length cap karte hain ya cycle-stealing chunks mein split karte hain. ARM AMBA AXI aur PCIe jaise fabrics is problem ko bounded transaction sizes se address karte hain.
Agar ek DMA transfer ek aise memory-mapped region ko target kare jo mapped/enabled nahi hua?
Bus access fault karta hai ya garbage padhta hai — DMA real bus transactions drive karta hai bilkul CPU ki tarah, toh ek unmapped ya protected address same error condition produce karta hai (bus error / abort). DMA ko memory map ke around koi special pass nahi milta.
Kya do DMA channels "simultaneously" run kar sakte hain?
Ek shared bus par exactly same cycle par nahi — sirf ek hi use drive kar sakta hai. Woh arbitration ke through interleave karte hain, toh woh time ke saath concurrent lagte hain lekin physically turns lete hain. True simultaneity ke liye independent bus segments ya ek multi-port fabric chahiye.
Recall Traps ka ek-line summary

Yahan har trap teen truths mein se ek par reduce hoti hai: DMA per byte hands-off hai, poori tarah nahi; DMA ek bus master hai jo share karta hai; aur DMA cache ko bypass karta hai, toh coherency aapki zimmedari hai.