This page assumes you know nothing. We build every word the CXL (Compute Express Link) parent note throws at you — cache, coherency, MESI, PCIe, GT/s, snoop, cache line, address space — starting from a picture of a chip talking to memory.
Picture: a long row of numbered lockers. Address = locker number.
Why the topic needs it: the parent note writes things like MemRd to address 0x2_000_0000. That is nothing more than "fetch the data in locker number two-hundred-something-million".
Why CXL cares: CXL memory expanders let the processor use locker numbers beyond the ones served by its own local RAM. The lockers physically live in another box, but the processor names them the same way — see the figure.
0x means "the number after me is in hexadecimal (base-16)"
it is just a counting shorthand engineers use; 0x1000 is the decimal number 4096.
Reaching all the way to the memory wall is slow. So each processor keeps a small, very fast copy of the data it uses most, right next to it.
Picture: the worker keeps a sticky note of the numbers they're using. Reading the sticky note is instant; walking to the locker wall is slow.
Why the topic needs it: the parent says "CPU has a 64-byte cache line at address 0x1000". That is one sticky note holding the 64 bytes starting at locker 4096.
To enforce coherency, each sticky-note copy carries a label describing how trustworthy and how private it is. There are exactly four labels.
The golden rule these states enforce:single-writer OR multiple-readers. Either exactly one holder may write (M or E), or many may read but none may write (S). Never two writers.
Why the topic needs it: every CXL.cache example is a walk through these four labels — a locker goes M → S when a GPU asks to read it, etc. Once you know the labels, that walk is obvious.
Which state means "my copy is dirty and memory is stale"?
Modified (M)
Which state lets many caches hold the same line for reading?
How does one processor find out whether another has a private, possibly-dirty copy? It asks. That question is called a snoop.
Picture: the worker holds up a locker number and shouts across the room, "Anyone holding #57? If it's dirty, give it here!"
Why the topic needs it: the parent's opcodes SnpData, SnpInv are exactly these shouts — Snp = snoop, Data = "give me the data", Inv = "invalidate your copy". A snoop-based coherency protocol is just this shouting done in hardware at nanosecond speed.
With the vocabulary above, the parent's three protocols collapse to one picture: who is caching whose memory.
Two related standards worth knowing: DMA-(Direct-Memory-Access) (moving data without bothering the CPU), and the pre-CXL rivals Gen-Z-and-CCIX. CXL's memory-expansion angle relates to HBM-(High-Bandwidth-Memory) and to NUMA-(Non-Uniform-Memory-Access), where different memory is at different distances/latencies — exactly the world CXL manages.
Read it top-down: the plain picture of processor + memory splits into two families — addressing/caching (left) and the physical wire (right) — and both must be understood before the CXL topic at the bottom makes sense.
