Is page pe assume kiya gaya hai ki aap kuch nahi jaante. Hum har word build karenge jo CXL (Compute Express Link) parent note mein use hota hai — cache, coherency, MESI, PCIe, GT/s, snoop, cache line, address space — ek chip ke memory se baat karne ki picture se shuru karke.
Picture: numbered lockers ki ek lambi line. Address = locker number.
Topic ko iske zaroorat kyun hai: parent note mein likha hota hai jaise MemRd to address 0x2_000_0000. Yeh bas itna hai — "locker number do-sau-kuch-crore mein data fetch karo".
CXL ko iske zaroorat kyun hai: CXL memory expanders processor ko woh locker numbers use karne dete hain jo uske apne local RAM se bahar hain. Lockers physically doosre box mein hain, lekin processor unhe same tarah se naam leta hai — figure dekho.
0x ka matlab hai "mere baad wala number hexadecimal (base-16) mein hai"
yeh bas ek counting shorthand hai jo engineers use karte hain; 0x1000 decimal number 4096 hai.
Memory wall tak jaana slow hai. Isliye har processor apne paas jo data sabse zyada use karta hai uski ek chhoti, bahut fast copy rakhta hai.
Picture: worker jinhe numbers use karne hain unka ek sticky note rakhta hai. Sticky note padhna instant hai; locker wall tak chalna slow hai.
Topic ko iske zaroorat kyun hai: parent kehta hai "CPU has a 64-byte cache line at address 0x1000". Yeh ek sticky note hai jo locker 4096 se shuru hone wale 64 bytes hold karta hai.
Coherency enforce karne ke liye, har sticky-note copy pe ek label hota hai jo describe karta hai ki woh kitni trustworthy aur kitni private hai. Exactly chaar labels hain.
In states ka golden rule:single-writer YA multiple-readers. Ya toh exactly ek holder write kar sakta hai (M ya E), ya bahut saare read kar sakte hain lekin koi nahi likh sakta (S). Kabhi do writers nahi.
Topic ko iske zaroorat kyun hai: CXL.cache ka har example in chaar labels ke through ek walk hai — ek locker M → S jaata hai jab GPU use read karna chahta hai, etc. Ek baar labels pata hon, woh walk obvious ho jaati hai.
Kaun si state ka matlab hai "meri copy dirty hai aur memory stale hai"?
Modified (M)
Kaun si state kaafi caches ko reading ke liye same line hold karne deti hai?
Ek processor ko kaise pata chalta hai ki doosre ke paas ek private, possibly-dirty copy hai? Woh poochhta hai. Woh question snoop kehlaata hai.
Picture: worker ek locker number uthata hai aur kamre mein chillaata hai, "Koi #57 hold kar raha hai? Agar dirty hai, toh yahan do!"
Topic ko iske zaroorat kyun hai: parent ke opcodes SnpData, SnpInv exactly yahi chillane hain — Snp = snoop, Data = "mujhe data do", Inv = "apni copy invalidate karo". Ek snoop-based coherency protocol bas yahi chillana hai jo hardware mein nanosecond speed pe hota hai.
Upar di gayi vocabulary ke saath, parent ke teen protocols ek picture mein collapse ho jaate hain: kaun kiska memory cache kar raha hai.
Do related standards jaanne wale hain: DMA-(Direct-Memory-Access) (CPU ko pareshan kiye bina data move karna), aur pre-CXL rivals Gen-Z-and-CCIX. CXL ka memory-expansion angle HBM-(High-Bandwidth-Memory) se relate karta hai aur NUMA-(Non-Uniform-Memory-Access) se bhi, jahan alag memory alag distances/latencies pe hoti hai — exactly woh duniya jise CXL manage karta hai.
Ise top-down padho: processor + memory ki plain picture do families mein split hoti hai — addressing/caching (left) aur physical wire (right) — aur dono ko samajhna zaroori hai before ki neeche CXL topic samajh aaye.
