Multicore vs manycore designs: Question bank — Hinglish deep dive

6.1.4 · D5 · Hardware › Parallelism & Multicore › Multicore vs manycore designs

Yeh ek misconception-hunting page hai parent topic ke liye. Yahan koi bhari arithmetic nahi hai — neeche har sawaal ek aisi belief ko target karta hai jo sach lagti hai lekin gaur karne par toot jaati hai. Prompt padho, apna jawab zor se bolo, phir reveal karo.

Pehle yeh vocabulary zaroori hai

Koi bhi trap samajhne se pehle, hamein har symbol aur acronym ko khud kamaana hoga jo woh use karta hai. Neeche kuch bhi assume nahi kiya gaya hai.

Latency = ek akele task ko start se finish tak kitna time lagta hai (ek kaam par stopwatch).
Throughput = ek second mein kitne tasks finish hote hain (poori factory ko dekhta ek counter).

Ek multicore chip low latency chase karta hai; ek manycore chip high throughput chase karta hai. Is page ke lagne wale har trap ki asli wajah in dono ko confuse karna hi hai.

Figure dekho. Left par, ek mota pipe ek single ball ko fast move karta hai — yeh low latency hai, multicore ideal. Right par, kaafi patli pipes hain aur har ek ball ko dheere move karti hai, lekin itni saari ek saath ki zyada balls per second niklengi — yeh high throughput hai, manycore ideal. Same total "pipe material" (transistors), bilkul ulte tarike se kharche gaye.

Do aur acronyms "why" section mein aate hain, isliye unhe abhi define karte hain, baad mein nahi:

Do pieces of hardware area-budget traps mein blame hote hain, toh unse abhi milo:

Amdahl's formula, poori tarah likhi hui

Woh ek equation jis par yeh poora page tika hai woh hai Amdahl's Law. Hum ise yahan state karte hain taaki tumhe kabhi click karke door na jaana pade:

Graph dikhata hai kyun serial fraction "killer" hai. Har curve $P$ ko fix karta hai aur $N$ (cores) ko horizontal axis par badhne deta hai. Dekho har curve ek ceiling mein flat ho jaata hai: jab $N \to \infty$ toh $P / N$ term gayab ho jaata hai, chhod ke $Speedup \to \frac{1}{1 - P}$ . $P = 0.95$ bhi (top curve) kabhi $1/0.05 = 20 \times$ cross nahi kar sakta. Flat part ke baad cores add karna kuch nahi kharidta — yahi trap hai jinhe aadhe sawaal spring karte hain.

True ya false — justify karo

More cores ka matlab hamesha more speedup hota hai

False — fixed serial fraction

(1 - P)

ke saath, Amdahl's Law

1/ (1 - P)

ki ceiling par flat ho jaata hai; agar kisi kaam ka 30% serial hai (

P = 0.7

) toh infinite cores bhi zyada se zyada

1/0.3 = 3.33 \times

dete hain.

Ek manycore chip hamesha ek multicore chip se faster hota hai

False — sirf regular data-parallel kaam ke liye; ek single branchy thread par multicore core (zyada instructions finished per clock, higher clock) har instruction ko faster khatam karta hai, isliye woh bahut bade margin se jeetta hai.

Har manycore core har multicore core se faster hai kyunki unki sankhya zyada hai

False — bilkul ulta: individual manycore cores simple, in-order, aur low-clock hote hain, sirf 1–2 instructions per cycle khatam karte hain. Aggregate throughput zyada hai; per-core latency buri hai.

Core count double karne se throughput double hota hai

Sirf tab agar utilization fixed rahe — lekin jab cores badhte hain toh woh ek shared memory bus ke liye compete karte hain, isliye har ek data ke liye zyada intezaar karta hai (Memory Hierarchy), aur cores ke beech Cache Coherence messages multiply hote hain; dono utilization giraa dete hain (zyada idle time), isliye throughput

2 \times

se kam badhta hai.

Ek multicore CPU ko sirf caches shrink karke manycore CPU mein badla ja sakta hai

False — area budget dekhte hain: ek bade core mein cache sirf ek hissa hoti hai; out-of-order scheduler aur branch predictor baaki ke bade blocks hain. Sirf cache free karne se woh in place rehte hain, isliye aapko utna area recover nahi milta ki dozens of simple cores fit ho sakein. Teeno ko strip karna padega.

Manycore designs ko branch prediction ki sabse kam zaroorat hoti hai

True — woh stalls ko doosre ready thread par switch karke hide karte hain instead of guess karne ke ki branch kis taraf jaayegi; haazaaron threads available hone se, ek mispredicted branch bas us ek thread ko park kar deta hai jabki baaki ALUs ko busy rakhte hain.

Transistor budget ek soft constraint hai jise better design se exceed kiya ja sakta hai

False — die area process node aur cost target se fix hota hai; control logic par kharcha har mm² ek aisa mm² hai jo cores par nahi kharch ho sakta. Yeh ek hard, conserved tradeoff hai.

Ek single-threaded program ek 512-core manycore chip par ek 8-core multicore chip se faster run karta hai

False — ek single thread effectively ek core use karta hai (

N = 1

); manycore ka ek kamzor core multicore ke ek strong core se buri tarah haar jaata hai. Baaki 511 idle cores ek thread ki madad nahi kar sakte.

Hyper-Threading se aapko double cores milte hain

False — yeh ek physical core ko do thread contexts hold karne deta hai taaki stalls hide ho sakein; yeh existing hardware ki utilization badhata hai, lekin

N

(real cores) unchanged rehta hai.

Error dhundho

"Amdahl's speedup formula prove karta hai ki manycore chips bekar hain, kyunki serial code sabko cap kar deta hai."

Error scope mein hai — Amdahl ek single fixed-size job ko bound karta hai apne

(1 - P)

term se; manycore un jobs par shine karta hai jo (almost) 100% parallel hain (

P \approx 1

) aur saath hi kaafi independent jobs ek saath run karne par, jahaan per-job serial cap barely laagu hoti hai.

"Humne apne database ke liye GPUs choose kiye kyunki unke paas thousands of cores hain."

Galat workload — database queries pointer-chasing, branchy, aur locks se bhari hoti hain (sequential critical sections); yeh simple manycore pipelines ko punish karta hai. Yeh ek classic multicore-wins case hai.

"Manycore cores power waste karte hain kyunki unki sankhya itni zyada hai."

Har simple core sirf ~0.1–1 W draw karta hai versus ek complex core ke liye 15–50 W; per-useful-operation, manycore aksar zyada energy-efficient hota hai — dekho Power Consumption. Count matter karta hai, per-op cost se kam.

"Kyunki

P = 0.95

max speedup

20 \times

deta hai, ek 8-core chip already 12 cores waste karta hai."

20 \times

asymptotic ceiling hai (curve ka flat part,

N \to \infty

par);

N = 8

1/ ((1 - 0.95) + 0.95/8)

mein plug karo aur tumhe lagbhag

5.9 \times

milega, 20 se bahut neeche — toh woh 8 cores sab useful kaam kar rahe hain. Limit ko current value se confuse mat karo.

"L3 cache add karna ek manycore chip mein usse multicore chip bana dega."

Ek shared cache ek feature hai, defining line nahi. Line yeh hai: few strong cores vs many weak cores; cache wala ek manycore chip still manycore hai.

"Ek task jo 100% parallel hai,

N

cores par exactly

N \times

speedup lega."

Sirf ideally — formula

1/ (0 + 1/ N) = N

tabhi deta hai jab utilization perfect ho (ALUs kabhi idle nahi); real speedup memory bandwidth, synchronization, aur interconnect traffic se cap hota hai, isliye A100 example theoretical ~6912× ke ~4000× tak pahunchta hai.

"Thread switching sasta hai, isliye multicore chips memory stalls hide karne ke liye freely threads switch karte hain."

Ulta hai — multicore par ek switch thousands of cycles cost karta hai (software-managed), isliye woh ek 100-cycle stall hide nahi kar sakta; manycore hardware mein ~1 cycle mein switch karta hai, aur yahi exactly hai kaise woh stalls hide karta hai.

Why questions

Hum ek aisa chip kyun nahi bana sakte jo per-thread maximally fast bhi ho AUR maximally parallel bhi?

Fixed transistor/area budget — out-of-order scheduler, bade caches, aur branch predictor jo ek core ko fast banate hain, exactly wahi area hai jisko aapko zyada cores add karne ke liye chahiye. Budget ek taraf ya doosri taraf kharch hota hai.

Manycore memory latency ko caches ki bajaye threads se kyun hide karta hai?

Jab hundreds of threads ready hote hain, toh ek stalled thread simply swap out ho jaata hai (hardware mein sasta) jabki baaki compute karte hain; yeh ALUs (calculating circuits) ko busy rakhta hai bina scarce area bade caches par kharche — dekho Memory Hierarchy.

GPUs "same instruction, many threads" execution kyun favour karte hain?

Yeh SIMT hai — threads ke ek group mein ek instruction stream share karna ek single control unit ko kaafi ALUs drive karne deta hai, isliye almost saare transistors arithmetic mein jaate hain — data-parallel kaam ke liye perfect. Dekho SIMD vs MIMD.

Single-thread performance chase karna abhi bhi kyun worthwhile hai chahe ek 8-core machine par?

Serial fraction

(1 - P)

ek core par run karta hai aur, Amdahl ke mutabik, total time dominate karta hai jab parallelism badhta hai; ek fast serial core us part ko shrink karta hai jisko koi bhi amount of Thread-Level Parallelism nahi chhu sakta.

Branch-heavy code specifically manycore designs ko kyun punish karta hai?

SIMT mein, ek group ke threads ko same instruction follow karni padti hai; jab branches threads ko alag paths par bhejte hain (divergence), toh hardware har path ko serially run karta hai, un ALUs ko waste karta hai jo lockstep mein run karne ke liye meant the.

Heterogeneous chips kuch bade cores ko bahut saare chhote cores ke saath kyun pair karte hain?

Har workload ko sahi engine se match karne ke liye — latency-critical serial code ke liye bade cores, throughput-heavy parallel code ke liye chhote cores/accelerators — ek style ko dono karne ke liye force karne ki bajaye, yahi idea hai Heterogeneous Computing ke peeche.

Serial fraction

(1 - P)

ko "killer" kyun kehte hain?

Kyunki yeh hard ceiling set karta hai — jab

N \to \infty

toh

P / N

term gayab ho jaata hai aur speedup

1/ (1 - P)

approach karta hai; koi bhi parallel hardware serial time nahi hataa sakta, isliye ek tiny serial slice quietly sab kuch cap kar deta hai.

Edge cases

Speedup kya hai jab

P = 0

(kuch bhi parallel nahi), kisi bhi number of cores par?

Exactly

1 \times

— Amdahl deta hai

1/ ((1 - 0) + 0/ N) = 1/1 = 1

; extra cores idle baithe hain, isliye multicore ya manycore koi farq nahi karta.

Speedup kya hai jab

P = 1

(fully parallel),

N

cores par?

Ideally exactly

N \times

—

1/ (0 + 1/ N) = N

; yeh woh akela case hai jahan zyada cores linearly scale karte hain, aur yahi precisely manycore sweet spot hai.

Throughput ka kya hota hai jab utilization

0

approach karti hai (saare threads memory par stalled)?

Throughput core count se regardless zero ki taraf collapse karta hai — kyunki throughput directly utilization se (ALUs ki busy-fraction) scale karta hai, ek bandwidth-starved manycore chip aise behave karta hai jaise uske paas almost koi core nahi hai.

Agar kisi kaam mein chip ke paas cores se zyada independent threads hain toh?

Manycore ise achhi tarah tolerate karta hai — extra threads queue karte hain aur instantly fill in karte hain jab doosre stall hote hain, utilization badhata hai; multicore ko unhe software mein high switching cost par time-slice karna padta hai.

Agar kisi kaam mein cores se bahut kam threads hain (jaise 512 cores par 2 threads)?

510 cores idle ho jaate hain — throughput hardware waste hota hai (utilization near zero), aur un do threads ko ek fast multicore core se better serve kiya jaata. Galat tool kaam ke liye.

Kisi bhi parallel chip par ek single-thread program ka "speedup" kya hai?

Cores axis par

1 \times

— yeh ek core use karta hai (

N = 1

); jeetne wali cheezein sirf us core ke khud ke clock aur instruction throughput se aati hain, parallelism se nahi, yahi wajah hai kyun multicore har core ko strong rakhta hai.

Jab simple cores ki sankhya limit ke bina badhti jaaye, toh Amdahl ki jagah real speedup ko actually kya limit karta hai?

Physical limits lete hain over — memory bandwidth, interconnect/network-on-chip traffic, aur coherence overhead (Cache Coherence) curve ko theoretical linear line se bahut pehle flat kar dete hain.

Recall Quick self-test

Woh single sentence jo in aadhe traps ko unlock karti hai ::: Multicore latency optimise karta hai (ek task fast); manycore throughput optimise karta hai (many tasks per second) — zyaadatar "wrong intuitions" in dono goals ko swap kar deti hain. Woh ek law jo har parallel speedup ko cap karta hai ::: Amdahl's Law, $Speedup = 1/ ((1 - P) + P / N)$ — serial fraction $(1 - P)$ ceiling $1/ (1 - P)$ set karta hai chahe kitne bhi cores $N$ add karo. P, N aur utilization kya stand karte hain ::: $P$ = parallel fraction (0–1), $N$ = number of cores, utilization = woh fraction of time jitna ALUs actually kaam kar rahe hain instead of idling ke.