Parent note Multicore vs Manycore Designs padhne se pehle, tumhe usme aane wale har symbol ko earn karna hoga. Yeh page har ek ko zero se build karta hai, ek aisi order mein jahan har idea pehle wale par lean karta hai. Yahan yeh assume nahi kiya gaya ki tumne pehle kabhi CPU diagram dekha hai.
Ek chip (woh kala square jo tumhe computer kholne par dikhta hai) andar bahut saare aaise workers side by side rakh sakta hai. Yahi is chapter ka poora subject hai: kitne workers, aur har ek kitna clever hai.
Figure dekho. Left par, ek bada worker ek badi desk ke saath (bahut saare tools). Right par, bahut saare chhote workers choti choti desks ke saath. Same total floor space. Yahi tradeoff hai, ek baar draw kiya taaki tum kabhi na bhuulo.
Parent note mein aisi cheezein likhi hain jaise Atotal, Acore, Acache. Letter A ka matlab sirf area hai — koi cheez chip surface par kitni jagah leti hai.
Chote subscripts (letter ke neeche ke chhote words) sirf batate hain ki hum kaunsa area mean kar rahe hain:
Subscript
Yeh kaunsa area name karta hai
Atotal
poori chip ka floor space (cost & manufacturing se fixed)
Acore
ek core ki calculating machinery ke liye jagah
Acache
ek core ki fast local memory ke liye jagah
Acontrol
"smart" logic ke liye jagah (prediction, reordering)
Ainterconnect
wiring ke liye jagah jo cores ko baat karne deti hai
N is pure topic ka star hai. Har formula disguise mein ek hi sawaal poochta hai: N badhne par kya hota hai?
Yahan area idea se seedha pehla payoff milta hai. Agar poori chip Atotal hai aur har core ko Asimple chahiye, toh tum jitne cores fit kar sakte ho woh hai:
N=Aper coreAtotal
Yeh bas division = "chhoti cheez badi cheez mein kitni baar fit hoti hai?" hai — usi tarah jaise tum pizza ke slices count karne ke liye pizza ka area slice ke area se divide karte ho. Ek tiny core (0.2mm2) ek fat core (10mm2) se 50× zyada baar fit hota hai, jo exactly parent ka "1 complex core ≈ 50 simple cores" hai.
Har worker ke paas ek metronome imagine karo. Ek 4GHz metronome ek second mein 4 billion baar tick karta hai; worker har tick par ek baar act kar sakta hai.
IPC = ek tick mein kitna kaam hota hai (worker ke kitne haath hain)
Figure mein ek clever core dikhta hai (har tick mein 4 boxes clear) aur saath mein chaar simple cores (har ek tick mein 1 box). Notice karo: chaar simple cores milke bhi 4 boxes per tick clear karte hain — lekin sirf tab jab chaar independent kaam dene ke liye hoon. Yeh thought pakad ke rakho; yahi wajah hai ki manycore ko "data parallelism" chahiye.
Yeh is pure topic mein sabse gehri confusion hai, isliye hum dono ko ek picture ke saath define karte hain.
Figure mein do checkout lanes dekho. Ek express lane ek lightning-fast cashier ke saath low latency deta hai — tumhare items seconds mein scan ho jaate hain. Daas slow cashiers ki ek row high throughput deti hai — store overall per minute zyada customers serve karta hai, chahe har customer thoda zyada wait kare.
Parent note ka throughput formula ab padhne layak hai:
Throughput=Ncores×fclock×IPC×Utilization
Seedhe shabdon mein: (kitne workers hain) × (har ek ke ticks per second) × (har ek ke jobs per tick) × (actually kaam karne ka fraction). Yeh bas un chaar ideas ko multiply karna hai jo ab tumhare paas hain.
Ek kaam ko ek bar samjho. Uska kuch hissa "shareable" colour karo (length P) aur kuch "akele karna hai" (length 1−P). Shareable part N workers ko dene se woh P/N ho jaata hai. Akela wala part kabhi nahi shrinks.
Yeh akeli picture hi speedup formula hai:
Speedup=(1−P)+NP1
(1−P) term = woh zidd wala akela part (kabhi nahi shrinks).
P/N term = shareable part, N mein split.
Poori derivation Amdahl's Law mein hai; yahan tumhe sirf dekhte hi har symbol pehchanna hai.
Upar se neeche padho: core aur area ideas number-of-cores tradeoff create karte hain; clock, IPC, utilization throughput lens build karte hain; latency vs throughput aur Amdahl's P decide karte hain ki kisi diye gaye kaam ke liye kaunsi philosophy jeetti hai.