Question bank — Average memory access time (AMAT)

False. Start from the expected value $(1-m)HT+m(HT+MP)$; the $HT$ appears in both branches, so it factors out as $HT[(1-m)+m]=HT$. Hit time is unconditional; only $MP$ carries the factor $m$.

True. Treat AMAT $=HT+m\cdot MP$ as a function of $m$; its slope $\frac{d(\text{AMAT})}{dm}=MP>0$ is a positive constant, so AMAT is strictly increasing in $m$ and any decrease in $m$ strictly decreases AMAT.

True. Substituting $m=0$ gives $HT+0\cdot MP=HT$; with no misses the penalty term is identically zero, so every access costs exactly one cache access.

False. Substituting $m=1$ gives $HT+1\cdot MP=HT+MP$, not $MP$ — because our convention makes $MP$ the extra cost, a guaranteed miss still pays the hit access first. See Miss Penalty & Main Memory Latency.

False. Compare no-L2 AMAT $=H{T}_{L1}+m_{L1}\cdot M{P}_{DRAM}$ with two-level $=H{T}_{L1}+m_{L1}(H{T}_{L2}+m_{L2}M{P}_{DRAM})$. L2 helps only if $H{T}_{L2}+m_{L2}M{P}_{DRAM}<M{P}_{DRAM}$, i.e. if $H{T}_{L2}<(1-m_{L2})M{P}_{DRAM}$; violate this and AMAT rises.

False. The outer factor $m_{L1}$ already scales down to the accesses that reached L2, so the inner $m_{L2}$ must be local; using the global rate $m_{L1}{m}_{L2,local}$ inside would apply the $m_{L1}$ discount twice. See Multi-level Cache Hierarchy.

Usually false. Concretely with $HT=1$, $m=0.05$, $MP=100$: AMAT $=6$; halving $HT$ to $0.5$ gives $5.5$ (−0.5), but halving $m$ to $0.025$ gives $3.5$ (−2.5). The $m\cdot MP$ term ($=5$ of the $6$ ns) dominates, so attacking $m$ or $MP$ wins by far.

True. As $m\to 0$ the term $m\cdot MP\to 0$, so AMAT $\to HT$; e.g. $m=0.01$, $MP=100$ gives $HT+1$, dominated by $HT$ when $HT$ is a few ns. This is why fast $HT$ matters for L1, kept near-total-hit by Locality of Reference.

False. Global $=m_{L1}\times m_{L2,local}$ with $0\le m_{L1}\le 1$; multiplying a non-negative number by a factor $\le 1$ cannot increase it, so global $\le$ local (equal only in the degenerate case $m_{L1}=1$).

The miss branch is wrong: a miss costs $HT+MP$, not $MP$ alone, since you still searched the cache first. The correct expected value $(1-m)HT+m(HT+MP)$ collapses to $HT+m\cdot MP$.

The L1 miss penalty is the whole L2 subsystem's AMAT ($H{T}_{L2}+m_{L2}M{P}_{L2}$), not the raw DRAM latency — most L1 misses are caught by L2 and never reach DRAM.

The inner $m_{L2}$ must be local; plugging in the global rate $m_{L1}{m}_{L2,local}$ applies the L1 filtering already carried by the outer $m_{L1}$ factor a second time.

In our convention $MP$ is the extra time beyond the hit access, so miss time is $HT+MP$; treating $MP$ as inclusive contradicts the formula and undercounts by exactly $HT$.

It matters through the product $m_{L1}\times m_{L2}$, but with e.g. $m_{L1}{m}_{L2}=0.02$ and $MP=300$ ns the DRAM trips still add $6$ ns — often more than $HT$ itself, so you must compute, not eyeball.

Not necessarily — a bigger cache often has a slower $HT$ (see Cache Associativity & Hit Time tradeoff); if $HT$ rises by more than $m\cdot MP$ falls, AMAT rises despite the better hit rate.

Because every request first probes the cache before we know hit-or-miss, $HT$ is paid in both branches; in the expected value $(1-m)HT+m(HT+MP)$ that shared term factors to a constant $+HT$, independent of $m$.

Reaching DRAM requires missing at L1 and then missing at L2; using local rates, the fraction of all accesses that reach DRAM is (fraction missing L1) $\times$ (fraction of those missing L2) $=m_{L1}\times m_{L2,local}$ — this is a definitional counting fact about nested conditional fractions, not a statistical independence assumption.

In $HT+m\cdot MP$, if $MP$ is 100–200× larger than $HT$, then even a small $m$ makes $m\cdot MP$ exceed $HT$; e.g. $m=0.05,MP=100,HT=1$ gives a $5$ ns miss contribution versus $1$ ns hit — the rare-but-huge term dominates the mean.

Over $N$ accesses, total time $=(1-m)N\cdot HT+mN\cdot (HT+MP)$; dividing by $N$ to get the per-access average yields exactly $(1-m)HT+m(HT+MP)$ — AMAT is literally the long-run mean time per access, which is the definition of expected value.

The outer $m_{L1}$ already restricts to the accesses forwarded to L2, so the inner probability must be conditioned on "given we reached L2, do we miss?" — that conditional fraction is precisely the local miss rate; using global would double-condition.

Even a $5\%$ L1 miss rate times a $200$ ns DRAM trip adds $0.05\times 200=10$ ns per access; routing those misses through a fast L2 (say $H{T}_{L2}=10$, $m_{L2}=0.2$) replaces the $200$ with $10+0.2\times 200=50$, cutting the contribution from $10$ to $2.5$ ns.

AMAT sets the average memory-stall time per access; multiplying by accesses-per-instruction gives stall cycles per instruction, which the CPU Performance Equation adds to the base CPI — so AMAT directly inflates total execution time.

Just $H{T}_{L1}$ — with $m_{L1}=0$ the entire penalty bracket is multiplied by zero, so you only ever pay the fastest access time. This is the theoretical floor.

$H{T}_{L1}+1\cdot (H{T}_{L2}+0\cdot M{P}_{L2})=H{T}_{L1}+H{T}_{L2}$ — every access misses L1 and hits L2, so you always pay both levels' hit times and never touch DRAM.

AMAT $=HT+m\cdot 0=HT$, because misses cost nothing extra — a degenerate case where the hierarchy gives no penalty and the miss rate becomes irrelevant.

Miss rate is driven near $100\%$ by compulsory (cold) misses, so AMAT $\approx HT+MP$ — caches barely help without reuse. See Cache Miss Rate & Miss Types (3 Cs).

No — L2 helps only when $H{T}_{L2}+m_{L2}M{P}_{DRAM}<M{P}_{DRAM}$; if $H{T}_{L2}\ge M{P}_{DRAM}$ that inequality fails outright, so every L1 miss got slower and AMAT increases, defeating the hierarchy's purpose.

In $HT+m\cdot MP$, the $m\cdot MP$ term $\to 0$ while $HT$ stays fixed — confirming hit time is the floor and misses only ever add on top of it.