Write-through vs write-back: Foundations — Hardware deep dive

Before you can read the parent note, you must own every word it throws at you. This page builds each symbol from absolute zero: plain meaning → the picture → why the topic needs it. Nothing here assumes you've seen caches before beyond 5.4.01-CacheFundamentals.

The stage: two boxes holding the same number

Everything in this topic happens between exactly two storage boxes. Let's draw them before we name anything.

Symbol 1 — the address, and what "cached" means

The picture: in figure s01, the same house number 0x100 appears in both boxes. That's what "the location is cached" means — memory has the original, the cache has a copy.

Why the topic needs it: the whole "write problem" only exists because two boxes name the same address. A write must decide which copies to update.

Symbol 2 — hit and miss

The picture: figure s02 shows two doorbells. On a hit (mint arrow) the CPU gets its answer from the cache immediately. On a miss (coral arrow) the request travels all the way down to memory and back.

Why the topic needs it: the parent's performance formulas all contain a Miss Rate term. Write-back's hidden cost (the eviction penalty) only fires on misses, so you cannot read those formulas without this word.

Symbol 3 — the cache line (the unit that moves)

The picture: think of a bookshelf that only moves in full shelves, never single books. Even to update one book, the whole shelf slides out and back.

Why the topic needs it: this is the reason the dirty bit is per line, not per byte (parent Mistake 2), and the reason a writeback sends 64 bytes even if you changed 1 byte.

Symbol 4 — the dirty bit

The picture: figure s03 shows two lines with a little flag beside each. A raised coral flag (=1) means "unsaved changes here — don't lose me." A lowered mint flag (=0) means "already saved, safe to overwrite."

Why the topic needs it: write-back's entire strategy is "delay the memory write, but remember which lines still owe memory an update." The dirty bit is that memory. Without it, write-back couldn't tell which evictions need a writeback.

Symbol 5 — eviction (making room)

The picture: a full parking lot. A new car arrives; some parked car must leave first. If the leaving car has unsaved changes (dirty=1), you must first drive it to the memory garage (writeback) before the new car can park.

Why the topic needs it: eviction is when write-back finally pays memory. The parent's " $2 \times T_{memory}$ " read-miss penalty is exactly: one memory access to write the dirty old line out + one to fetch the new line in.

Symbol 6 — consistency (synchronized vs stale)

Why the topic needs it: this is the axis the two policies sit on. Write-through keeps the two boxes always equal; write-back allows them to disagree for a while. When many cores each cache the same address, staleness becomes the coherence problem — but that's a later note.

Symbol 7 — the timing symbols ( $T$ , $≫$ , ns)

The parent uses letters with subscripts as stopwatch readings. They are not scary — each is just "how long this one step takes."

Formula Reading the timing symbols

Symbol	Plain meaning	Typical value
$T_{cache}$	time to write the cache copy	~1 ns
$T_{memory}$	time for one memory access	~100 ns
$T_{write-through}$	total time of a write-through store	~101 ns
$T_{write-back}$	total time of a write-back store (hit)	~1 ns
$≫$	"is hugely bigger than"	—

Why $≫$ matters: the parent writes $T_{memory} ≫ T_{cache}$ to justify dropping the small term. Because 100 ns is ~100× bigger than 1 ns, $1 + 100 \approx 100$ : the cache time is a rounding error. That single inequality is why write-through "costs a memory access" and write-back "costs nothing" (on a hit).

Symbol 8 — rates and probabilities ( $R_{write}$ , $P_{dirty}$ , Miss Rate)

The picture: imagine 1000 evictions passing a gate. If $P_{dirty} = 0.5$ , then 500 of them carry a raised dirty flag and must detour through memory; the other 500 are clean and just vanish.

Why the topic needs it: these turn "sometimes we pay memory" into a number. The parent's bus-traffic result — write-back sends only $Miss Rate \times P_{dirty} = 0.05 \times 0.5 = 0.025$ of the writes to the bus, i.e. 1 in 40 — is pure multiplication of these fractions.

Symbol 9 — the write buffer

The picture: a mailbox. You drop a letter (1 ns) and walk away; the postal van (memory) collects later. You only wait if the mailbox is full — that's the "stall."

Why the topic needs it: it's how write-through hides its 100 ns cost most of the time, which is why the parent says write-through "can be competitive." The stall condition $R_{write} > N / T_{memory}$ just says: if letters arrive faster than the van clears the box, the box overflows and you wait.

How these foundations feed the topic

Read top-to-bottom: two boxes holding one number create the mismatch; hit/miss and the dirty bit decide when memory gets fixed; timing and probability symbols turn that decision into the numbers the parent computes.

Equipment checklist

What does "0x100" mean in Cache[0x100] = 42?

The cache's copy of memory house 0x100 currently holds the value 42 — it's a label/address, not arithmetic.

Roughly how much slower is memory than cache?

About 100× — memory ~100 ns, cache ~1 ns.

What is a cache hit vs a miss?

Hit = data already in cache (~1 ns); miss = not there, must fetch from memory (~100 ns).

What is a cache line and how big is it typically?

The fixed chunk (≈64 bytes) that cache and memory always exchange — never a single byte.

What does the dirty bit = 1 mean?

This line was written and now differs from memory; it must be written back before being discarded.

Why is the dirty bit per line and not per byte?

Memory transfers happen a whole line at a time, and per-byte tracking would cost too much hardware.

What is eviction, and when does write-back finally touch memory?

Kicking out an old line to make room; a dirty evicted line is written back to memory at that moment.

What does

T_{memory} ≫ T_{cache}

let us do?

Drop the tiny cache time, since 1 + 100 ≈ 100 — the memory access dominates.

What do Miss Rate and

P_{dirty}

measure?

Fraction of accesses that miss, and fraction of evicted lines that are dirty — both are probabilities 0 to 1.

What does a write buffer of depth N do, and when does it stall?

Queues write-through stores so the CPU continues; it stalls only when writes arrive faster than it can drain to memory (buffer full).