Exercises — Write-through vs write-back

(a) Write-through: memory is updated on every single write (a store to a cached line writes cache and memory at the same time). (b) Write-back: memory is updated only when a dirty line is evicted (replaced) — the store itself only touches the cache and sets the dirty bit.

No. Dirty bit $=0$ means the cache copy and memory copy are identical, so writing back would just copy the same bytes onto themselves — pure waste. The line is simply discarded and the new line loaded. Memory write only happens when dirty bit $=1$.

1. Memory transactions are line-granular. A memory write moves a whole $64$-byte line in one burst, so you cannot send "just the 1 changed byte" cheaply anyway.
2. Per-byte dirty bits cost too much. A $64$-byte line would need $64$ dirty bits instead of $1$ — that's $64\times$ the flag storage and logic for essentially no traffic saving.

Write-through: cache write + memory write happen together, but the store isn't "done" until memory acknowledges: $T_{\text{WT}}=T_{\text{cache}}+T_{\text{mem}}=1+100=101\mathbf{ns}$ Write-back: only the cache is touched; memory is left stale: $T_{\text{WB}}=T_{\text{cache}}=1\mathbf{ns}$ Speedup on this one write: $101/1=101\times$ (parent rounds this to "$\approx 100\times$" by dropping the $+1$).

Write-through — every write pays the full memory latency: $500\times (T_{\text{cache}}+T_{\text{mem}})=500\times 101=50,500\mathbf{ns}$ Write-back — $500$ cheap cache writes, then one memory write on eviction: $500\times T_{\text{cache}}+1\times T_{\text{mem}}=500\times 1+100=600\mathbf{ns}$ Speedup: $50,500/600\approx 84\times$. The many repeated writes are why write-back wins: it amortizes one memory write over all $500$.

Clean victim: just fetch the new line. $T_{\text{clean}}=T_{\text{fetch}}=T_{\text{mem}}=100\mathbf{ns}$ Dirty victim: you must first write the old dirty line back to memory, then fetch the new one — two memory accesses (the two arrows in the figure): $T_{\text{dirty}}=T_{\text{writeback}}+T_{\text{fetch}}=100+100=200\mathbf{ns}$ So a dirty eviction doubles the miss penalty. This is the price write-back pays for its cheap writes.

Write-through: every store hits the bus → ${\text{Bus}}_{\text{WT}}=1$ per store. Write-back: a store only reaches the bus if it causes a miss and evicts a dirty line: ${\text{Bus}}_{\text{WB}}=\text{Miss Rate}\times P_{\text{dirty}}=0.05\times 0.50=0.025\text{ per store}$ Ratio: $\frac{{\text{Bus}}_{\text{WB}}}{{\text{Bus}}_{\text{WT}}}=\frac{0.025}{1}=\frac{1}{40}$ Write-back cuts memory-write traffic to $1/40$ (a $40\times$ reduction). This is the argument for write-back on the DRAM bus where bandwidth is scarce.

Compute the "writes in flight during one memory latency": $R_{\text{write}}\times T_{\text{mem}}=0.05\times 100=5$. $P_{\text{stall}}=\max (0,\frac{5-8}{5})=\max (0,-0.6)=0$ No stall. The buffer holds $8$ pending writes, but only $5$ arrive per drain time, so it never fills. The buffer fully hides memory latency here.

Writes in flight: $R_{\text{write}}\times T_{\text{mem}}=0.2\times 100=20$. $P_{\text{stall}}=\frac{20-8}{20}=\frac{12}{20}=0.6$ $T_{\text{avg}}=T_{\text{cache}}+P_{\text{stall}}\times T_{\text{mem}}=1+0.6\times 100=61\mathbf{ns}$ Now writes arrive $4\times$ faster than the buffer drains, so it saturates $60\%$ of the time and the CPU eats most of the memory latency. The buffer only helps up to its depth.

Write-through: each of the $k$ writes pays cache + memory: $T_{\text{WT}}(k)=k(T_{\text{cache}}+T_{\text{mem}})=101k$ Write-back: $k$ cheap cache writes + one memory write at eviction: $T_{\text{WB}}(k)=k{T}_{\text{cache}}+T_{\text{mem}}=k+100$ Crossover (write-back cheaper when $T_{\text{WB}}<T_{\text{WT}}$): $k+100<101k\Rightarrow 100<100k\Rightarrow k>1$ So for any $k\ge 2$ writes to the same line, write-back wins; at $k=1$ (write-once) they are essentially tied ($T_{\text{WB}}=101$, $T_{\text{WT}}=101$). This is the mathematical statement of "write-back needs temporal locality."

Benefit (coherence): write-through to L2 keeps L2 always up-to-date, so a snooping coherence protocol can service other cores' reads straight from L2 without hunting for a dirty L1 copy — this simplifies the invalidation/ordering rules discussed under memory consistency. Cost: every L1 store now generates L1→L2 traffic (bandwidth ↑) even for data reused many times, partly giving up write-back's traffic savings on the L1→L2 link.

Write-back: $T_{\text{WB}}=1+0.10(100+0.40\times 100)=1+0.10(100+40)=1+0.10(140)=1+14=15\mathbf{ns}$ Write-through (buffer never stalls ⇒ $P_{\text{stall}}=0$): $T_{\text{WT}}=T_{\text{cache}}+P_{\text{stall}}\times T_{\text{mem}}=1+0=1\mathbf{ns}$ Winner: here write-through is faster on average ($1$ ns vs $15$ ns)! The reason: at $10\%$ miss rate the write-back miss/writeback overhead ($14$ ns) outweighs the buffer-hidden write-through cost. Latency is not the whole story — write-back still wins on bus traffic (Ex 3.1) and never depends on a non-stalling buffer, so under a saturated buffer (Ex 3.3) the verdict flips. Policy choice depends on which metric your system is bottlenecked by.

Policy: write-through + no-write-allocate.

• Why not write-back? Each address is written once ($k=1$). From Ex 4.1, write-back gives zero amortization benefit at $k=1$ — you pay one memory write per line either way. Its extra machinery (dirty bits, writeback logic, dirty-eviction double penalty from Ex 2.3) buys nothing.
• Why no-write-allocate? The data is never re-read, so fetching a line into cache on a write miss (write-allocate) is wasted bandwidth — you'd fetch $64$ bytes just to overwrite them and never read them. No-write-allocate sends the write straight to memory, no fetch.
• Buffer: add a deep write buffer to coalesce sequential writes and hide latency for the streaming pattern (Ex 3.2 shows a buffer fully hides latency when writes don't out-race the drain). This is exactly the "write-once / streaming" case the parent's Mistake 1 steel-mans.