Write-through vs write-back: Exercises — Hinglish deep dive

5.4.6 · D4 · Hardware › Memory Hierarchy & Caches › Write-through vs write-back

Shuru karne se pehle, ek shared cost model jo hum har jagah reuse karenge taaki koi number surprise na kare:

Level 1 — Recognition

Exercise 1.1

Ek-ek sentence mein batao, (a) write-through aur (b) write-back ke under main memory kab update hoti hai.

Recall Solution

(a) Write-through: memory har ek write par update hoti hai (ek cached line mein store cache aur memory dono ko simultaneously write karta hai). (b) Write-back: memory tabhi update hoti hai jab ek dirty line evict (replace) hoti hai — store khud sirf cache ko touch karta hai aur dirty bit set karta hai.

Exercise 1.2

Ek cache line ka dirty bit = 0 hai aur use eviction ke liye choose kiya gaya hai. Kya memory mein write hoga? Kyun?

Recall Solution

Nahi. Dirty bit $= 0$ matlab cache copy aur memory copy identical hain, toh write back karna toh wohi bytes unpe hi copy karna hoga — bilkul waste. Line simply discard kar di jaati hai aur nayi line load hoti hai. Memory write tabhi hoti hai jab dirty bit $= 1$ ho.

Exercise 1.3

Write-back mein, dirty bit byte per nahi balki line per track hoti hai. Do hardware reasons batao.

Recall Solution

Memory transactions line-granular hote hain. Ek memory write poori $64$ -byte line ko ek burst mein move karta hai, isliye "sirf 1 changed byte bhejo" ka option cheaply available nahi hai.
Per-byte dirty bits bahut zyada cost karti hain. Ek $64$ -byte line ko $1$ ki jagah $64$ dirty bits chahiye honge — essentially koi traffic saving nahi hogi jabki flag storage aur logic $64 \times$ ho jaayega.

Level 2 — Application

Exercise 2.1

Har policy ke under ek single store jo cache mein hit kare ka write latency compute karo.

Recall Solution

Write-through: cache write + memory write saath hote hain, lekin store tab tak "done" nahi hota jab tak memory acknowledge na kare: $T_{WT} = T_{cache} + T_{mem} = 1 + 100 = 101 ns$ Write-back: sirf cache touch hoti hai; memory stale rehti hai: $T_{WB} = T_{cache} = 1 ns$ Is ek write par Speedup: $101/1 = 101 \times$ (parent isko " $\approx 100 \times$ " tak round karta hai $+ 1$ drop karke).

Exercise 2.2

Ek program ek hi same cache line mein $500$ baar write karta hai, phir line dirty evict hoti hai. Har policy ke liye total write-related time do.

Recall Solution

Write-through — har write memory latency pay karta hai: $500 \times (T_{cache} + T_{mem}) = 500 \times 101 = 50, 500 ns$ Write-back — $500$ saste cache writes, phir eviction par ek memory write: $500 \times T_{cache} + 1 \times T_{mem} = 500 \times 1 + 100 = 600 ns$ Speedup: $50, 500/600 \approx 84 \times$ . Baar baar repeat hone wale writes ki wajah se write-back jeet ta hai: yeh ek memory write ko $500$ par amortize karta hai.

Exercise 2.3

Ek read miss ek aise set par hoti hai jiska victim line dirty hai. Write-back cache mein clean victim wali read miss ke mukable mein penalty explain karo aur quantify karo. Figure dekho.

Recall Solution

Clean victim: bas nayi line fetch karo. $T_{clean} = T_{fetch} = T_{mem} = 100 ns$ Dirty victim: pehle purani dirty line ko memory mein write back karna padega, phir nayi line fetch karni padegi — do memory accesses (figure mein do arrows): $T_{dirty} = T_{writeback} + T_{fetch} = 100 + 100 = 200 ns$ Toh dirty eviction miss penalty ko double kar deti hai. Yahi woh price hai jo write-back apne saste writes ke liye chukati hai.

Level 3 — Analysis

Exercise 3.1

Ek workload ke liye: $Miss Rate = 5%$ , $P_{dirty} = 50%$ . Har store instruction ek "write" hai. Write-back ke memory-bus writes ka write-through se ratio compute karo.

Recall Solution

Write-through: har store bus ko hit karta hai → $Bus_{WT} = 1$ per store. Write-back: store tabhi bus tak pahunchta hai jab woh miss cause kare aur ek dirty line evict kare: $Bus_{WB} = Miss Rate \times P_{dirty} = 0.05 \times 0.50 = 0.025 per store$ Ratio: $\frac{Bus _{WB}}{Bus _{WT}} = \frac{0.025}{1} = \frac{1}{40}$ Write-back memory-write traffic ko $1/40$ tak kaat deta hai ( $40 \times$ reduction). Yahi argument hai write-back ke liye DRAM bus par jahan bandwidth scarce hoti hai.

Exercise 3.2

Write-through depth $N = 8$ ke write buffer ke saath. Write rate $R_{write} = 0.05$ writes/ns (har $20$ ns mein ek write), $T_{mem} = 100$ ns. Kya CPU stall karega? $P_{stall} = max (0, \frac{R _{write} T _{mem} - N}{R _{write} T _{mem}})$ use karo.

Recall Solution

"Ek memory latency ke dauran writes in flight" compute karo: $R_{write} \times T_{mem} = 0.05 \times 100 = 5$ . $P_{stall} = max (0, \frac{5 - 8}{5}) = max (0, - 0.6) = 0$ Koi stall nahi. Buffer $8$ pending writes hold kar sakta hai, lekin ek drain time mein sirf $5$ aate hain, toh yeh kabhi fill nahi hota. Buffer yahan memory latency poori tarah hide kar leta hai.

Exercise 3.3

Wohi buffer ( $N = 8$ ), lekin ek write-heavy burst $R_{write} = 0.2$ writes/ns (har $5$ ns mein ek write) tak badha deta hai. $P_{stall}$ aur average write time $T_{avg} = T_{cache} + P_{stall} \times T_{mem}$ compute karo.

Recall Solution

Writes in flight: $R_{write} \times T_{mem} = 0.2 \times 100 = 20$ . $P_{stall} = \frac{20 - 8}{20} = \frac{12}{20} = 0.6$ $T_{avg} = T_{cache} + P_{stall} \times T_{mem} = 1 + 0.6 \times 100 = 61 ns$ Ab writes buffer ke drain hone se $4 \times$ tezi se aa rahe hain, toh yeh $60%$ time saturate hota hai aur CPU zyaadatar memory latency jhelta hai. Buffer sirf apni depth tak hi help karta hai.

Level 4 — Synthesis

Exercise 4.1

Crossover banao. Write-back mein, ek line ko eviction se pehle $k$ baar likha jaata hai (eviction hamesha dirty). $T_{WT} (k)$ aur $T_{WB} (k)$ likho, phir woh $k$ nikalo jis par write-back sasta ho jaata hai. $T_{cache} = 1$ , $T_{mem} = 100$ use karo.

Recall Solution

Write-through: $k$ writes mein se har ek cache + memory pay karta hai: $T_{WT} (k) = k (T_{cache} + T_{mem}) = 101 k$ Write-back: $k$ saste cache writes + eviction par ek memory write: $T_{WB} (k) = k T_{cache} + T_{mem} = k + 100$ Crossover (write-back tab sasta jab $T_{WB} < T_{WT}$ ): $k + 100 < 101 k \Rightarrow 100 < 100 k \Rightarrow k > 1$ Toh kisi bhi $k \geq 2$ writes ke liye same line par, write-back jeet ta hai; $k = 1$ par (write-once) dono essentially tie karte hain ( $T_{WB} = 101$ , $T_{WT} = 101$ ). Yahi "write-back ko temporal locality chahiye" ka mathematical statement hai.

Exercise 4.2

Ek design L1 ke liye write-back use karta hai lekin L1→L2 ke liye write-through. Coherence ke liye ek benefit aur ek cost do. Coherence idea ko sahi vault topic se link karo.

Recall Solution

Benefit (coherence): L2 tak write-through L2 ko hamesha up-to-date rakhta hai, toh ek snooping coherence protocol doosre cores ki reads ko seedha L2 se serve kar sakta hai bina dirty L1 copy dhundhe — isse memory consistency ke under discuss ki gayi invalidation/ordering rules simplify hoti hain. Cost: ab har L1 store L1→L2 traffic generate karta hai (bandwidth ↑) chahe data baar baar reuse ho, isse L1→L2 link par write-back ki traffic savings kuch had tak kho jaati hain.

Level 5 — Mastery

Exercise 5.1

Full latency model. Write-back with write-allocate. Given: Miss Rate $= 10%$ , $P_{dirty} = 40%$ , $T_{cache} = 1$ , $T_{fetch} = T_{writeback} = 100$ . $T_{avg-write} = T_{cache} + MissRate (T_{fetch} + P_{dirty} T_{writeback})$ use karo. Phir write-through ka $T_{avg}$ compute karo (maano uska 8-deep buffer kabhi stall nahi karta). Kaun jeet ta hai, aur kitne se?

Recall Solution

Write-back: $T_{WB} = 1 + 0.10 (100 + 0.40 \times 100) = 1 + 0.10 (100 + 40) = 1 + 0.10 (140) = 1 + 14 = 15 ns$ Write-through (buffer kabhi stall nahi karta ⇒ $P_{stall} = 0$ ): $T_{WT} = T_{cache} + P_{stall} \times T_{mem} = 1 + 0 = 1 ns$ Winner: yahan average par write-through faster hai ( $1$ ns vs $15$ ns)! Reason: $10%$ miss rate par write-back ka miss/writeback overhead ( $14$ ns) ek well-buffered write-through ke hidden cost se zyada hai. Latency poori kahani nahi hai — write-back phir bhi bus traffic par jeet ta hai (Ex 3.1) aur kabhi non-stalling buffer par depend nahi karta, toh saturated buffer ke under (Ex 3.3) verdict ulat jaata hai. Policy choice is baat par depend karti hai ki tumhara system kis metric par bottleneck hai.

Exercise 5.2

Design task. Tum ek GPU streaming kernel ke liye cache bana rahe ho: har address exactly ek baar likha jaata hai, kabhi re-read nahi hota, gigabytes flow ho rahe hain. Write policy aur allocation policy choose karo, aur tumhare compute kiye numbers se justify karo.

Recall Solution

Policy: write-through + no-write-allocate.

Write-back kyun nahi? Har address ek baar likha jaata hai ( $k = 1$ ). Ex 4.1 se, write-back $k = 1$ par zero amortization benefit deta hai — tum ya woh, har line ke liye ek memory write pay karte ho. Uski extra machinery (dirty bits, writeback logic, Ex 2.3 se dirty-eviction double penalty) kuch kaam nahi aati.
No-write-allocate kyun? Data kabhi re-read nahi hota, toh write miss par line ko cache mein fetch karna (write-allocate) wasted bandwidth hai — tum $64$ bytes fetch karte sirf unhe overwrite karne ke liye aur kabhi read nahi karte. No-write-allocate write ko seedha memory mein bhejta hai, koi fetch nahi.
Buffer: sequential writes ko coalesce karne aur streaming pattern ke liye latency hide karne ke liye deep write buffer add karo (Ex 3.2 dikhata hai ki buffer tab latency poori tarah hide karta hai jab writes drain ko out-race na karein). Yahi parent ke Mistake 1 mein steel-man kiya gaya "write-once / streaming" case hai.