VLIW architectures: Foundations — Hardware deep dive

Before you can read the parent note, you need to know what a processor, an instruction, a cycle, a functional unit, and a dependency actually are — as pictures, not jargon. Below, every word and symbol the parent note leans on is built from nothing. Read top to bottom; each block only uses words defined above it.

1. What a processor does, as a picture

Look at the figure. The tall stack on the left is a program: a list of instructions the processor reads top to bottom. The clock at the bottom ticks; on every tick, one row of work happens. The picture defines the whole rhythm of the topic — everything the parent note says about "per cycle" and "lock-step" is just "what happens between two ticks."

Why the topic needs this: VLIW's entire selling point is doing more per tick. You cannot understand "more per tick" until you can see a single tick.

2. Functional units — the workers inside

The figure shows four workers standing side by side, exactly matching the parent note's 4-slot machine: two ALUs (blue), one memory port (orange), and one branch/FP worker (green). Each has an empty tray in front of it. A single instruction hands each worker one job to do this tick.

3. A "slot" and the Very Long Instruction Word

4. Registers and data dependencies — the reason not everything can run together

The figure shows the three flavours of dependency the parent note names. Follow the arrows:

RAW (Read After Write): A writes r1, then B reads r1. B truly needs A's result — this is a real dependency you can never remove.
WAR (Write After Read): A reads r1, then B overwrites r1. B must wait only so it doesn't stomp on the value before A looked at it. This is a fake clash caused by reusing the same box name.
WAW (Write After Write): A writes r1, then B also writes r1. Only the last write should survive; again a fake clash from name reuse.

5. Compiler and static scheduling

6. The Greek and bracket symbols used in the scheduling formulas

The parent note's later formulas throw several symbols at you at once. Here they are, each earned:

Recall Why the max, not the sum?

Question: In $II_{m i n} = max (ResMII, RecMII)$ , why take the maximum and not add them? ::: Because both are lower bounds on the same quantity (ticks per iteration). Satisfying the bigger one automatically satisfies the smaller. Adding would over-count — you don't pay both floors, you pay whichever is higher.

7. How these foundations feed the topic

Read the map bottom-up: ticks make workers meaningful, workers make slots meaningful, slots make the wide word, and dependencies plus renaming are what the compiler must reason about to fill that word — which is exactly static scheduling, and its quality is measured by II.

Equipment checklist

Cover the right side; say the answer before revealing.

A clock cycle is ::: one tick of the processor's metronome; one step of work happens per tick.
A functional unit is ::: a hardware worker that does one kind of job (ALU, memory, branch, FP).
Why does one memory port cap the array loop? ::: Only one load/store can pass through it per tick, so memory ops must be spread across separate instructions.
A slot is ::: a labelled box in one instruction naming the job for one specific functional unit.
$n$ in the VLIW word means ::: the number of slots (issue width); $n = 4$ in the parent machine.
A NOP is ::: "this worker does nothing this tick" — a paid idle worker.
A register is ::: a tiny named value box inside the processor, like r1.
RAW is ::: Read After Write — a true dependency that no trick can remove.
WAR and WAW are ::: fake clashes from reusing a register name; removable by register renaming.
Who does register renaming in VLIW? ::: The compiler, at compile time (not the hardware).
Static scheduling means ::: the parallel plan is decided once, at compile time, before running.
$⌈ x ⌉$ means ::: round x up to the next whole number, because you can't use a partial tick.
$max_{r} f (r)$ means ::: try every choice of r and keep the largest, because the worst bottleneck sets the pace.
The initiation interval II is ::: ticks between starting one loop iteration and the next; smaller is faster.
$II_{m i n} = max (ResMII, RecMII)$ because ::: both are lower bounds on the same quantity; you must satisfy both, so take the larger.

Back to the parent: VLIW architectures.