Question bank — VLIW architectures

Functional unit ::: a piece of hardware that does one kind of work (an integer adder, a load/store port, a multiplier). Picture a single cook at one station. Slot ::: a fixed field inside one wide instruction that tells one functional unit what to do this cycle. Picture one compartment of a meal-kit tray. NOP ::: "no operation" — the placeholder you put in a slot when the compiler found no useful work for that unit this cycle. An empty tray compartment. Static scheduling ::: the compiler decides, before the program ever runs, which operations go in which slot of which cycle. Nothing is re-decided at runtime. Interlock ::: hardware that stalls an instruction until its inputs are ready. VLIW deliberately removes these and trusts the compiler instead.

False ::: The compiler discovers parallelism at compile time and freezes it into the instruction word; VLIW hardware just routes each slot to its unit with plain combinational logic — no runtime dependency search exists on the chip.

True ::: Slots are fixed-length fields, so unused slots are filled with NOP bit-patterns that still take up space — this is exactly why low-parallelism code hurts VLIW code density.

False ::: With no interlocks the hardware never stalls to wait, so a missed RAW gives a wrong result (the reader gets stale data), not a slow one. Correctness now lives in the compiler.

False ::: Slots are an upper bound on parallelism, not a guarantee. A dependent chain (like the Fibonacci loop) fills one slot per cycle and gets ≈1× — VLIW exploits existing parallelism, it cannot manufacture it.

False ::: There is exactly one load/store functional unit, so at most one memory op per cycle. Two loads must occupy two consecutive instruction words no matter how many empty ALU slots sit beside them.

False ::: WAR (write-after-read) and WAW (write-after-write) are false dependencies caused by reusing register names. Renaming to fresh registers removes them; only RAW (a genuine data flow) must be preserved.

True ::: Every slot of one wide word issues in the same cycle and the whole word retires together — there is no per-unit reorder buffer letting one unit run ahead of another.

False ::: Superscalar spends O(n²)-ish area on wakeup/select, renaming and reorder buffers to schedule in hardware; VLIW moves that job to the compiler, so its scheduling hardware is tiny by comparison.

The flaw ::: Both can be built to the same issue width; VLIW's advantage is simpler, lower-power hardware, not more slots. Given equal width and equal parallelism they issue the same amount — the win is die area, power, and clock, not raw issue count.

The flaw ::: Cache misses and variable-latency memory are runtime effects the static schedule cannot foresee. A load assumed to take (say) 2 cycles that actually misses will stall the whole lock-step word, so runtime data still matters.

The flaw ::: You cannot put independence there if the program does not contain four independent ops at that point. The compiler must find or create it (loop unrolling, software pipelining), and if the code is a dependent chain it will honestly emit NOPs.

The flaw ::: That needs three memory ports; the machine has one. The compiler must reject this and serialise the memory ops across words — the single memory port is the throughput bottleneck.

The flaw ::: In VLIW there is no renaming hardware, so the compiler performs renaming itself during scheduling to break WAR/WAW hazards. The job doesn't disappear; it moves.

The flaw ::: Low utilisation reflects the program's lack of parallelism, not a hardware fault. A serial recurrence would run one-op-at-a-time on any machine; VLIW just makes the empty slots visible as NOPs.

fixed-length instruction words instead of variable-length ones? Because ::: Fixed positions let the decoder route each slot to its functional unit with simple combinational logic — no length-decoding or dynamic dispatch matrix. The price is the NOPs that pad unused slots.

Because ::: Wakeup/select and dependency-checking logic must compare every in-flight instruction against every other, so structures scale with pairs of instructions. Doubling the width more than doubles the logic — the motivation to offload it to the compiler.

Because ::: The compiler has unlimited time and global visibility of the whole program, while hardware must decide within a cycle using only a local window. Global static analysis can find parallelism hardware would miss.

${\text{II}}_{\min }=\max (\text{ResMII},\text{RecMII})$ a maximum of the two bounds, not a sum or minimum? Because ::: Both constraints must hold simultaneously — the schedule cannot be faster than what resources allow and cannot be faster than what recurrences allow. The tighter (larger) of the two governs, so you take the max.

Because ::: $\text{ResMII}=\lceil u_r/c_r\rceil$ with $c_r=1$ memory copy: if the loop needs several memory ops, the ceiling forces at least that many cycles per iteration. Extra ALU slots cannot carry memory traffic, so they just sit as NOPs.

zero parallel work for a cycle? One real op plus $(n-1)$ NOPs ::: This is the worst case for code density: you pay the full instruction-word width to do a single operation — sequential performance at wide-instruction memory cost.

$\text{Efficiency}=\frac{k}{n}\cdot \frac{b_{\text{RISC}}}{b_{\text{VLIW}}}$, what happens at the boundary $k=1$? Efficiency collapses ::: $k=1$ means one useful op per word, so the first factor is $1/n$ — you transmit $n$ slots' worth of bits per useful op. VLIW's density is worst exactly when parallelism is lowest.

$k$, and what does it represent? $k=n$ ::: Every slot holds a real operation, giving full utilisation. This is the ceiling the compiler chases via unrolling and software pipelining; real code usually lands somewhere between $1$ and $n$.

RecMII $=4$, then $1$ ::: $\lceil 4/1\rceil =4$ cycles per iteration for a tight self-recurrence; spreading the same latency over distance 4 gives $\lceil 4/4\rceil =1$, because the result is needed only four iterations later, leaving slack to overlap.

no dependency cycles at all — what bounds II? Only ResMII ::: With no recurrences, RecMII is effectively zero (no cycle to constrain), so the initiation interval is set purely by resource copies — the loop is limited by hardware ports, not by data feedback.

The entire word stalls ::: Because all slots issue and retire together, one late unit freezes the others — VLIW cannot let independent slots run ahead, which is the trade-off for having no reorder buffer.