Foundations — VLIW architectures

5.3.13 · D1 · Hardware › Advanced Microarchitecture › VLIW architectures

Parent note padhne se pehle, tumhe yeh jaanna zaroori hai ki ek processor, ek instruction, ek cycle, ek functional unit, aur ek dependency actually kya hoti hai — pictures ki tarah, jargon ki tarah nahi. Neeche, parent note jo bhi word aur symbol use karta hai wo sabse shuru se build kiya gaya hai. Upar se neeche padhte jao; har block sirf wahi words use karta hai jo usse pehle define ho chuke hain.

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1. Ek processor kya karta hai, ek picture ki tarah

Figure dekhte hain. Left mein lambi stack ek program hai: instructions ki ek list jo processor upar se neeche padhta hai. Neeche wali clock tick karti hai; har tick par kaam ki ek row hoti hai. Yeh picture poore topic ki rhythm define karti hai — parent note jo bhi "per cycle" aur "lock-step" ke baare mein kehta hai wo sirf "do ticks ke beech kya hota hai" hai.

Yeh topic ko kyun chahiye: VLIW ka poora selling point har tick par zyada karna hai. "Har tick par zyada" ko tab tak nahi samajh sakte jab tak ek single tick nazar na aaye.

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2. Functional units — andar ke workers

Figure mein chaar workers side by side khade hain, exactly parent note ki 4-slot machine se match karte hue: do ALUs (blue), ek memory port (orange), aur ek branch/FP worker (green). Har ek ke saamne ek khaali tray rakhi hai. Ek single instruction har worker ko is tick mein karne ke liye ek kaam deta hai.

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3. Ek "slot" aur Very Long Instruction Word

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4. Registers aur data dependencies — reason ki sab kuch ek saath nahi chal sakta

Figure mein teen tarah ki dependencies hain jo parent note name karta hai. Arrows follow karo:

• RAW (Read After Write): A r1 mein likhta hai, phir B r1 ko padhta hai. B ko sach mein A ka result chahiye — yeh ek asli dependency hai jo kabhi nahi hata sakti.
• WAR (Write After Read): A r1 padhta hai, phir B r1 ko overwrite karta hai. B ko sirf isliye wait karna padta hai taaki A ke dekhne se pehle value stomp na ho. Yeh ek nakli clash hai jo same box name reuse karne ki wajah se hoti hai.
• WAW (Write After Write): A r1 likhta hai, phir B bhi r1 likhta hai. Sirf aakhri write bachni chahiye; phir se ek nakli clash name reuse se.

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5. Compiler aur static scheduling

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6. Scheduling formulas mein use hone wale Greek aur bracket symbols

Parent note ke baad wale formulas ek saath kai symbols throw karte hain. Yeh raha har ek, samjha ke:

Recall Max kyun, sum kyun nahi?

Question: ${\text{II}}_{\min }=\max (\text{ResMII},\text{RecMII})$ mein, maximum kyun lete hain aur unhe add kyun nahi karte? ::: Kyunki dono ek hi quantity (ticks per iteration) par lower bounds hain. Bade ko satisfy karne se chhhota automatically satisfy ho jaata hai. Add karna over-count karna hoga — tum dono floors nahi pay karte, sirf jo zyada ho use pay karte ho.

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7. Yeh foundations topic ko kaise feed karte hain

Map ko neeche se upar padhte hain: ticks workers ko meaningful banate hain, workers slots ko meaningful banate hain, slots wide word banate hain, aur dependencies plus renaming woh cheezein hain jinke baare mein compiler ko sochna padta hai us word ko fill karne ke liye — yahi exactly static scheduling hai, aur uski quality II se measure hoti hai.

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Equipment checklist

Right side cover karo; jawab reveal karne se pehle khud bolo.

• Ek clock cycle hai ::: processor ke metronome ki ek tick; har tick par kaam ka ek step hota hai.
• Ek functional unit hai ::: ek hardware worker jo ek tarah ka kaam karta hai (ALU, memory, branch, FP).
• Ek memory port array loop ko kyun cap karta hai? ::: Sirf ek load/store har tick mein us se guzar sakta hai, isliye memory ops alag instructions mein spread karni padhti hain.
• Ek slot hai ::: ek instruction mein ek labelled box jo ek specific functional unit ke liye kaam ka naam batata hai.
• VLIW word mein $n$ ka matlab hai ::: slots ki sankhya (issue width); parent machine mein $n=4$.
• NOP hai ::: "yeh worker is tick mein kuch nahi karta" — ek paid idle worker.
• Register hai ::: processor ke andar ek chhota named value box, jaise r1.
• RAW hai ::: Read After Write — ek asli dependency jo koi trick nahi hata sakti.
• WAR aur WAW hain ::: register name reuse karne se nakli clashes; register renaming se hataye ja sakte hain.
• VLIW mein register renaming kaun karta hai? ::: Compiler, compile time par (hardware nahi).
• Static scheduling ka matlab hai ::: parallel plan ek baar, compile time par, run hone se pehle decide hota hai.
• $\lceil x\rceil$ ka matlab hai ::: x ko agale whole number tak round up karo, kyunki partial tick use nahi ho sakti.
• ${\max }_{r}f(r)$ ka matlab hai ::: r ki har choice try karo aur sabse badi rakho, kyunki worst bottleneck pace set karta hai.
• Initiation interval II hai ::: ek loop iteration shuru karne aur agla shuru karne ke beech ticks; chhota toh faster.
• ${\text{II}}_{\min }=\max (\text{ResMII},\text{RecMII})$ kyunki ::: dono ek hi quantity par lower bounds hain; dono satisfy karne zaroori hain, isliye jo bada hai use lo.

Parent par wapas jao: VLIW architectures.