Load-use hazard and stalls: Question bank — Hinglish deep dive

5.2.7 · D5 · Hardware › Processor Datapath & Pipelining › Load-use hazard and stalls

Shuru karne se pehle, ek shared vocabulary taaki har reveal saaf padhe:

True or false — justify karo

Load hamesha exactly ek bubble insert karta hai chahe baad wali instruction kuch bhi ho.

False — bubble consumer par depend karta hai. Agar next instruction independent hai (ya store hai jo MEM/WB→MEM forwarding use kar raha hai), toh zero bubbles zaroori hain.

Forwarding load-use hazards ke liye useless hai.

False — ek stall ke baad forwarding essential hai: yeh value ko MEM/WB→EX route karta hai. Forwarding ke bina ek nahi do stalls chahiye hote.

Load-use hazard mein stall isliye chahiye kyunki memory slow hai.

False — instant memory hone par bhi value sirf MEM ke end par defined hoti hai, consumer ke EX start ke liye ek workbench peeche. Yeh ek timing-alignment problem hai, speed problem nahi.

Stall load instruction ko freeze kar deta hai taaki woh baad mein finish ho.

False — load EX, MEM, WB se full speed par guzarta hai. Hum IF aur ID (consumer aur uske peeche wali sab) ko freeze karte hain, load ko kabhi nahi.

sw $2, 0($1) ke liye stall chahiye agar yeh lw $2, 4($1) ke turant baad ho.

False — store apna data register sirf MEM mein consume karta hai, jo store ke liye load ke MEM ke ek cycle baad aata hai. MEM/WB→MEM forward ise bina stall ke deliver karta hai.

Agar loaded register $0 hai, toh stall phir bhi insert hota hai.

False — $0 hardwired zero hai, isliye koi real data dependency nahi hai. Detection rule ki condition 3 (RegisterRt ≠ 0) stall ko suppress karti hai.

Ek stall aur compiler-inserted nop same pipeline timing produce karte hain.

True — dono consumer ko EX se pehle ek extra cycle dete hain, isliye load ki value MEM/WB→EX forward ke liye ready hoti hai. Fark sirf yeh hai ki kaun pay karta hai: hardware (stall) ya code size (nop).

Sirf load ke ALU result ko stall karna bhi hazard fix kar deta.

False — load koi ALU result produce nahi karta jise stall karein; uski useful value MEM se aati hai. Fix yeh hai ki dependent instruction ko delay karo, load ke ALU stage ko tweak nahi karo.

Load-use hazards aur ALU-ALU hazards dono ek hi tarike se solve hote hain.

False — ALU-ALU hazards sirf forwarding se fully solve hote hain (data EX ke end par exist karta hai, time par). Load-use hazards mein ek stall plus forwarding chahiye, kyunki EX shuru hone tak data ready nahi hota.

Error dhundho

"Jab bhi previous instruction ek load ho, stall insert karo."

Incomplete — load tabhi stall cause karta hai jab next instruction actually loaded register ko read kare. Independent following instruction ko koi bubble nahi chahiye.

"Detection rule: stall if ID/EX.MemRead = 1."

Missing conditions — tumhe register match bhi chahiye (loaded Rt next instruction ke Rs ya Rt ke equal ho) aur Rt ≠ 0. Sirf MemRead har load ko flag karta hai, sirf dangerous wale ko nahi.

"Stall ke dauran hum PC zero karte hain taaki koi nayi instruction fetch na ho."

Wrong action — hum PC ko freeze karte hain (uski value hold karte hain), zero nahi karte. Zeroing execution ko address 0 par jump karata; freezing simply next cycle mein same instruction re-fetch karta hai.

"Bubble banane ke liye hum IF/ID control signals clear karte hain."

Wrong register — hum ID/EX control signals zero karte hain taaki EX/MEM/WB path kuch na kare. IF/ID frozen (held) hota hai, cleared nahi.

"Load-use hazard ka matlab hai load ek stale register value padhta hai."

Wrong direction — load ke inputs theek hain; danger yeh hai ki load का output baad wali instruction consume karne se pehle produce nahi hota. Yeh producer-too-late problem hai, stale-input problem nahi.

"2-cycle stall se hum loads ke liye forwarding completely drop kar sakte hain."

Overkill hai lekin reasoning galat-flavoured hai — do stalls value ko register file (WB) tak pahunchne dete jab consumer ka ID re-read kare, forwarding avoid karte, lekin real designs ek stall + forwarding use karte hain kyunki cycles mein sasta hai.

"Stores ke data hazards kabhi nahi hote."

Jaisa bola gaya waise false hai — ek store can prior load par depend karta hai, lekin kyunki use value MEM mein (late) chahiye, forwarding ise bina stall ke cover karta hai. Hazard exist karta hai; sirf free mein resolve hota hai.

Why questions

Forwarding data stages ke beech move kar sakta hai lekin load-use case akele fix kyun nahi kar sakta?

Forwarding data spatially move karta hai (baad wale pipeline register se EX tak wapas) lekin use backwards in time nahi le ja sakta. Load ki value consumer ke EX start par simply exist hi nahi karti.

Detection unit IF aur ID ke beech kyun baithti hai, EX ke baad kyun nahi?

Yeh hazard ko tab pakadna chahiye jab dependent instruction EX mein commit karne se pehle ho, isliye yeh ID mein instruction (consumer) ko EX mein already wali instruction (load) ke against inspect karta hai. Yahi exactly IF/ID vs ID/EX boundary hai.

Stores preceding load ko tolerate karte hain jab ALU instructions nahi karte — kyun?

Store ko apna data register sirf MEM mein chahiye, jo load ke MEM ke ek cycle baad aata hai — MEM/WB→MEM forward ke liye kaafi late. ALU op ko EX mein chahiye, ek cycle pehle, jo bahut jaldi hai.

Condition 3 (Rt ≠ 0) rule ka hissa kyun hai?

Kyunki MIPS $0 hamesha zero padhta hai aur kabhi truly "produced" nahi hota, $0 padhne wali instruction ki koi real dependency nahi hai. Yahan stall skip karna ek faaltu bubble se bachata hai.

Ek stall cycle, do nahi, kyun kaafi hai jab forwarding exist kare?

Ek stall consumer ke EX ko load ke MEM complete hone ke baad wale cycle tak push karta hai, isliye freshly available MEM/WB value straight EX mein forward ho sakti hai. Yeh single delay exactly ek-cycle gap band karta hai.

Compiler scheduling CPI kyun reduce karta hai hardware change kiye bina?

Load ke turant baad wale slot mein ek independent instruction move karke (dekho Compiler instruction scheduling), consumer naturally ek cycle baad EX par pahunchta hai, isliye hardware ko kabhi bubble insert nahi karna padta.

Better cache load-use hazard kyun eliminate nahi karta?

Cache average memory latency kam karta hai lekin pipeline phir bhi load ki value end-of-MEM par schedule karti hai. Producer-consumer timing gap structural hai, cache kitni bhi fast ho uspar independent (dekho Memory hierarchy and cache).

Edge cases

lw $2, 0($1) ke baad add $4, $5, $6 (na $2 use karta hai).

No stall — register-match condition fail hoti hai, isliye hazard detection unit dono instructions ko full speed par flow karne deta hai.

lw $2, 0($1); lw $3, 0($2) — doosra load $2 ko apna base address use karta hai.

Stall required — doosra load apna address compute karne ke liye EX mein $2 chahiye, jo exactly load-use timing clash hai. Ek bubble, phir MEM/WB→EX forward.

lw $0, 0($1) ke baad add $4, $0, $3.

No stall — loaded register $0 hai, isliye condition 3 detection suppress karta hai. add waise bhi zero dekhta hai, isliye koi genuine dependency nahi.

lw $2, 0($1) jahan second-next instruction $2 use karti hai, lekin immediate next nahi karti.

No stall — ek independent instruction beech mein hone se consumer pehle se load ke MEM ke baad wale cycle mein EX reach karta hai, isliye ordinary MEM/WB→EX forwarding handle karta hai.

Ek load jiska consumer value ko dono source operands ke roop mein use karta hai (add $4, $2, $2).

Phir bhi sirf ek stall — match Rs ya Rt par fire hota hai; ise do baar use karna timing nahi badalta, sirf ek bubble chahiye.

Back-to-back loads same register mein: lw $2, 0($1); lw $2, 8($1).

In ke beech koi load-use stall nahi — doosra load $2 ko operand ke roop mein read nahi karta (uska base $1 hai), isliye koi dependency nahi; baad wali $2 value simply pehle wali ko overwrite karti hai.

Interrupt/flush stall cycle ke dauran aata hai.

Bubble EX mein already ek NOP hai, isliye wahan flush ka koi extra cost nahi; frozen IF/ID instruction flush par kisi bhi doosre ki tarah discard ho jaati hai (interaction Pipeline control signals ke under padha jaata hai).

Recall Quick self-check

Ek breath mein teen stall conditions ::: EX mein load (MemRead=1), uska Rt next instruction ke Rs ya Rt se match kare, aur woh Rt $0 na ho. Kaun freeze hota hai, kaun free chalta hai ::: PC + IF/ID freeze karo (consumer side); EX/MEM/WB (load) ko normally chalne do. Ek stall kyun, do nahi ::: forwarding MEM/WB→EX ke zariye remaining gap cover karta hai.