Structural hazards: Worked examples — Hardware deep dive

This page is the exhaustive worked-example companion to Structural hazards. The parent note built the idea of a resource conflict — two pipeline stages reaching for the same piece of hardware in the same clock tick. Here we chase down every kind of scenario that idea can produce and grind through the arithmetic, so no case ever surprises you in an exam.

If any word below feels unfamiliar (stage, cycle, stall, CPI), the parent note and Pipelining Fundamentals define them from zero. We reuse only those.

The scenario matrix

Every structural-hazard problem you will ever meet is one of the cells below. A "cell" is a class of situation — a combination of which resource conflicts, how the numbers behave, and what the question is really testing.

#	Cell (case class)	What makes it distinct	Covered by
A	Single unified memory (IF vs MEM)	Classic 2-way port conflict, non-zero load fraction	Example 1
B	Zero-hazard / degenerate input	Hazard probability $p = 0$ → no stalls at all	Example 2
C	Every-instruction hazard (limiting value)	Conflict on every cycle, $p = 1$	Example 3
D	Multi-cycle resource (penalty $s > 1$ )	Stall penalty bigger than one cycle	Example 4
E	Two independent hazard sources added	Memory hazard and functional-unit hazard together	Example 5
F	Fix-by-hardware comparison	Same program, before vs after adding a resource	Example 6
G	Real-world word problem	Embedded chip, throughput in MIPS	Example 7
H	Exam twist: "reorder to remove stall"	Scheduling instead of arithmetic	Example 8
I	Superscalar / port-count degenerate	Ports vs demanded accesses per cycle	Example 9

Before the numbers, one master formula that every cell uses.

Formula The one equation behind every cell

$CPI_{actual} = CPI_{ideal} + \sum_{i} (p_{i} \times s_{i})$ Read the second term as "stall cycles per instruction". Now the plain-words meaning of each symbol:

$CPI$ means clocks per instruction — the average number of clock cycles a typical instruction "costs". Lower is faster.
$CPI_{ideal} = 1$ for a simple single-issue pipeline (one instruction finishes each cycle when nothing goes wrong).
$p$ is the probability that a hazard hits per instruction — a fraction between $0$ and $1$ . When a hazard's rate equals some instruction-type fraction we may write, e.g., $p = f_{mem}$ — the letter $f$ just names where that probability comes from, it is still the same $p$ .
$s$ is the stall penalty — how many bubble cycles each hazard forces.
The $\sum_{i}$ ("sum over $i$ ") adds one term $p_{i} \times s_{i}$ for each distinct hazard source $i$ . Here $i$ ranges over the list of hazard types present, e.g. $i \in {memory, divider, register-port}$ . In Example 1 there is only one source ( $i$ takes one value), so the sum is a single term; in Example 5 there are two, so we add two terms.

Throughput fraction vs ideal $= \frac{CPI _{ideal}}{CPI _{actual}}$ (a number $\leq 1$ : the share of ideal speed you keep). Percentage slowdown $= 1 - \frac{CPI _{ideal}}{CPI _{actual}}$ (the share you lose). We keep these two phrasings strictly separate below.

Example 1 — Cell A: single unified memory

Forecast: guess — will CPI land near $1.1$ , $1.3$ , or $2.0$ ? (Hold your guess; we confirm it at the end of this example.)

The figure below is a pipeline timeline: each row is one instruction, each column one clock cycle, and each rounded box shows which stage that instruction occupies that cycle. Watch column 4 — that is where the collision happens.

Identify $p$ and $s$ . Every load/store, when in MEM, wants memory at the same tick a later instruction wants IF. So $p = f_{mem} = 0.30$ and $s = 1$ . Why this step? The formula needs a hazard probability and a penalty — nothing else. We must translate the English (" $30%$ are loads") into $p$ .
Apply the equation. $CPI = 1 + (0.30) (1) = 1.30$ . Why this step? Direct substitution into the master formula — the whole point of building it.
Percentage slowdown. Throughput fraction $= \frac{1.0}{1.30} = 0.769 \dots$ , so the pipeline keeps $76.9%$ of ideal speed. Percentage slowdown $= 1 - 0.769 = 0.231$ → $23.1%$ slower. Why this step? Performance is inversely proportional to CPI; the slowdown is the lost share, i.e. one minus the throughput fraction.

Forecast check: the answer $1.30$ is the middle guess — if you picked "near $1.3$ ", you were right.

Verify: Look at the figure — in cycle 4, I1 sits in MEM (coral) and I4 wants IF (lavender): one memory, two demands → exactly one bubble, matching $s = 1$ . Units: CPI is cycles/instruction; the throughput fraction $0.769$ and slowdown $0.231$ are dimensionless. ✓

Example 2 — Cell B: the degenerate zero case

Forecast: does removing all memory instructions kill the hazard entirely, or is there always some residual stall? (Decide now; the answer appears below.)

Set $p = 0$ . No instruction ever reaches MEM wanting data memory, so IF is never blocked. Why this step? This is the boundary of the model — we must confirm the formula behaves sanely when the hazard cannot occur.
Apply the formula. $CPI = 1 + (0) (1) = 1.0$ . Why this step? Shows the structural-hazard term vanishes; the pipeline is back to ideal.

Forecast check: the hazard is killed entirely — CPI drops to the ideal $1.0$ with zero residual stall. If you predicted "no residual stall", correct.

Verify: $1 + 0 = 1$ . A pipeline that never conflicts must have ideal CPI — the number confirms our intuition, so the model is trustworthy at its lower edge. ✓

Example 3 — Cell C: the limiting value $p = 1$

Forecast: if every instruction stalls once, does CPI double, or grow by less? (Guess, then read on.)

Set $p = 1$ , $s = 1$ . Every instruction incurs exactly one bubble. Why this step? Testing the upper extreme completes the range $0 \leq p \leq 1$ — no reader should wonder "what if it's always?".
Apply the formula. $CPI = 1 + (1) (1) = 2.0$ . Why this step? Confirms the worst case for a 1-cycle penalty is a doubling, not something wilder.
Percentage slowdown. Throughput fraction $= \frac{1.0}{2.0} = 0.5$ ; slowdown $= 1 - 0.5 = 0.5$ → the pipeline runs at half speed ( $50%$ slower).

Forecast check: CPI exactly doubles to $2.0$ — if you guessed "double", spot on.

Verify: With one bubble per instruction, effectively two cycles pass per completed instruction → CPI $= 2$ . Half throughput. Numbers agree. ✓

Example 4 — Cell D: a multi-cycle resource ( $s > 1$ )

Forecast: a rare event but expensive — bigger or smaller effect than Example 1's frequent-but-cheap hazard? (Predict, then check step 3.)

Read off $p$ and $s$ . $p = 0.08$ , $s = 3$ (three bubble cycles per divide). Why this step? The penalty is no longer $1$ ; we must not assume $s = 1$ blindly.
Apply the formula. $CPI = 1 + (0.08) (3) = 1 + 0.24 = 1.24$ . Why this step? Shows the product $p \times s$ is what matters, not either factor alone.
Compare with Example 1. Divider stall term $0.24 <$ memory stall term $0.30$ , so CPI $1.24 < 1.30$ : the rare-but-costly divider hurts slightly less than the frequent memory clash. Why this step? Exams love asking "which hazard costs more?" — the answer is always whichever has the larger $p \times s$ .

Forecast check: smaller effect — the divider ( $1.24$ ) hurts less than the memory hazard ( $1.30$ ). If you guessed "smaller", correct.

Verify: $0.08 \times 3 = 0.24$ ; $1 + 0.24 = 1.24$ . And $0.24 < 0.30$ , so $1.24 < 1.30$ , confirming the comparison. ✓

Example 5 — Cell E: two hazards stacked

Forecast: do the CPI increases just add, or do they multiply? (Pick one; the answer is in step 1.)

Stall terms add. Total stalls per instruction $= \sum_{i} p_{i} s_{i} = p_{1} s_{1} + p_{2} s_{2} = 0.30 + 0.24 = 0.54$ . Here the index $i$ ranges over the two sources ${memory, divider}$ . Why this step? Independent bubble sources contribute independent extra cycles — bubbles are counted, so they sum (this is exactly the $\sum_{i}$ in the master formula).
Apply the formula once. $CPI = 1 + 0.54 = 1.54$ . Why this step? The master formula's second term is the sum of all stall sources.

Forecast check: they add (not multiply) — the two stall terms $0.30$ and $0.24$ sum to $0.54$ .

Verify: $0.30 + 0.24 = 0.54$ ; $1 + 0.54 = 1.54$ . Notice this equals Example 1's CPI ( $1.30$ ) plus Example 4's extra ( $0.24$ ) — additivity holds. ✓

Example 6 — Cell F: before vs after a hardware fix

Forecast: is the speedup exactly $1.30 \times$ , or something smaller? (Guess, then see step 2.)

The figure below contrasts the two designs side by side: on the left, one shared memory box forces IF and MEM to fight; on the right, two separate cache boxes each serve one stage, so nothing collides.

New CPI. With separate caches, IF and MEM use different ports → $p_{mem} = 0$ , so $CPI_{new} = 1 + 0 = 1.0$ . Why this step? Adding hardware removes the resource conflict, driving that hazard's $p$ to zero.
Speedup factor. Performance $\propto 1/ CPI$ , so speedup $= \frac{CPI _{old}}{CPI _{new}} = \frac{1.30}{1.0} = 1.30$ . Why this step? Comparing two designs on the same program means comparing CPI directly (clock period unchanged). Here the speedup exceeds $1$ because the new machine is faster.

Forecast check: exactly $1.30 \times$ — the speedup equals the old CPI because the new CPI is $1.0$ .

Verify: $1.30/1.0 = 1.30 \times$ faster. The figure shows the Harvard split: two separate memory boxes, so cycle 4 has no clash. This is the Pipeline Stalls cure by construction. ✓

Example 7 — Cell G: real-world word problem

Forecast: will the throughput be nearer 200, 160, or 100 MIPS? (Guess; confirmed at the end.)

CPI. $CPI = 1 + 0.25 \times 1 = 1.25$ . Why this step? Throughput needs cycles-per-instruction first.
MIPS = clock / (CPI $\times 1 0^{6}$ ). Instructions per second $= \frac{cycles/second}{cycles/instruction} = \frac{200 \times 1 0 ^{6}}{1.25}$ . That gives instructions per second; dividing by $1 0^{6}$ converts "instructions per second" into "millions of instructions per second" (that is exactly what the M in MIPS means). So $\frac{200 \times 1 0 ^{6}}{1.25 \times 1 0 ^{6}} = 160$ MIPS. Why this step? We first get raw instructions/second, then rescale by $1 0^{6}$ purely as a unit change so the answer reads in millions.
Ideal MIPS. With CPI $= 1$ : $\frac{200 \times 1 0 ^{6}}{1.0 \times 1 0 ^{6}} = 200$ MIPS. Hazard cost $= 200 - 160 = 40$ MIPS. Why this step? The "cost" is the gap between ideal and actual throughput.

Forecast check: the answer is 160 MIPS — the middle option. If you guessed "near 160", correct.

Verify: $200/1.25 = 160$ ; $200 - 160 = 40$ MIPS lost. Units: (cycles/s)/(cycles/instr) = instr/s ✓. Sanity: $40/200 = 20%$ loss, matching $1 - 1/1.25 = 0.20$ . ✓

Example 8 — Cell H: the exam twist (reorder, no arithmetic)

Worked example Statement

In this classic single-adder microarchitecture the PC $+ 4$ increment is computed in the IF stage (the fetch stage bumps the program counter to the next instruction), and that same single adder is also the EX-stage arithmetic unit. The compiler cannot add hardware but can reorder independent instructions. Given the schedule below, is the structural stall in cycle 3 avoidable by reordering, and what is the real fix?

Cycle 3:  ADD in EX  (wants the adder)
Cycle 3:  next instr in IF (wants the adder for PC+4)

Forecast: can clever ordering ever dodge this, or is it fundamentally a hardware shortage? (Decide, then check step 2.)

Check if the conflict is order-dependent. IF (which computes PC $+ 4$ ) happens for every instruction every cycle. EX happens for arithmetic instructions. Reordering changes which instruction is in EX, not the fact that some instruction is always in IF. Why this step? Instruction-Level Parallelism scheduling only helps hazards that depend on which instructions are adjacent; this one does not.
Conclusion: not avoidable by reordering. Because IF demands the adder on every cycle, any instruction in EX collides. $p$ is structural, not schedule-dependent. Why this step? Distinguishes structural hazards (a physical shortage) from Data Hazards / Control Hazards (which reordering can soften).
The real fix: a dedicated PC incrementer. A separate cheap 32-bit adder just for PC $+ 4$ in the IF stage removes the sharing, dropping this hazard's $p$ to $0$ . Why this step? Matches the parent note's "add a cheap adder" resolution — cost of one adder ≪ cost of endless stalls.

Forecast check: it is fundamentally a hardware shortage — reordering cannot dodge it; only a dedicated adder does. If you guessed "hardware shortage", correct.

Verify: The logical claim: if a resource is demanded every cycle by one stage, no permutation of instructions removes the clash → reordering fails; only extra hardware works. Consistent with the parent's definition of a structural (resource) hazard. ✓ (No numeric check — this cell is conceptual by design.)

Example 9 — Cell I: superscalar port-count degenerate case

Forecast: with only 3 read ports but 4 reads demanded, does it stall, and by how much? (Guess, then follow the count.)

Count demanded vs available reads. Demand $= 4$ reads this cycle; supply $= 3$ read ports. Shortfall $= 1$ read that cannot be served. Why this step? A port hazard is purely "demand $>$ supply" — count both sides.
Stall to serialise the extra access. The one unserved read must wait, so the register access spreads over $2$ cycles instead of $1$ : penalty $s = 1$ bubble. Why this step? Three ports can serve at most $3$ reads in one cycle; a $4$ th read has no port this cycle, so by definition it must slip to the next cycle — that slip is the single stall cycle.
Write check. Writes demanded $= 1$ , write ports $= 1$ → supply meets demand, no write conflict this cycle. Why this step? We must cover every port type; the reader should never assume writes are fine without checking supply vs demand there too.
Feed into the master formula. Let $p_{rd}$ be the fraction of cycles this read-port shortage occurs, with $s = 1$ . The read-port hazard contributes one term $p_{rd} \times 1$ to the sum $\sum_{i} p_{i} s_{i}$ (here index $i = register-port$ ). Taking the worst case where every issue clashes, $p_{rd} = 1$ , so $CPI = 1 + (1) (1) = 2.0$ . Why this step? The page promised every cell routes through $CPI = 1 + \sum_{i} p_{i} s_{i}$ ; the port hazard is simply one more $p_{i} s_{i}$ term, and $p = 1$ gives its worst case.

Forecast check: yes it stalls — by exactly 1 cycle, pushing worst-case CPI to 2.0. If you guessed "stalls by 1", correct.

Verify: Reads $4 > 3$ ports → hazard, minimum $1$ stall cycle. Writes $1 \leq 1$ → OK. Worst-case CPI $= 1 + 1 = 2$ . The fix (add a 4th read port) sets demand $\leq$ supply, drives $p_{rd}$ to $0$ , and removes the stall — matching the parent's "more ports" strategy. ✓

Recall Quick self-test on the cells

Which cell has the larger CPI, "frequent-cheap" ( $p = 0.3, s = 1$ ) or "rare-costly" ( $p = 0.08, s = 3$ )? ::: Frequent-cheap: $0.30 > 0.24$ , so CPI $1.30 > 1.24$ . Compare the products $p \times s$ . Can instruction reordering remove a structural hazard that hits every cycle? ::: No — it is a hardware shortage, not an ordering problem; only extra hardware (or accepting the stall) helps. A program with $p = 0$ on single-port memory has what memory-hazard CPI? ::: Exactly $1.0$ — the stall term vanishes.