Foundations — Structural hazards

Before you can understand why two instructions collide over hardware, you must own every word in that sentence: what a "pipeline" is, what a "stage" is, what a "clock cycle" is, what a "resource" is, and the tiny bit of arithmetic (CPI) that measures the damage. We build each from nothing.

1. The clock cycle — the heartbeat

The picture: imagine a drummer beating steadily. Every beat, all dancers move one position. Nobody moves between beats. The processor is the same — work only "counts" on the beat.

Why the topic needs it. A structural hazard is defined as two things happening "in the same clock cycle." If you cannot picture a single discrete tick, you cannot picture two instructions arriving on the same tick. The word "simultaneous" in the parent note literally means "on the same beat of this drum."

We will write a specific cycle as $t=1,2,3,\dots$ — just counting beats. That's all the symbol $t$ means here: which beat we are on.

2. The instruction and its five stages

To run one instruction fully, the classic design breaks the work into five steps, called stages. Think of building a sandwich on a five-station counter:

The picture: five stations in a row. An instruction enters at IF and walks left-to-right, one station per clock cycle (there's our drumbeat again).

Why the topic needs it. Two of these stages — IF and MEM — both reach into memory. Hold that thought; it is the single most common structural hazard, and you cannot see the collision until you can name the two stages that cause it. See Pipelining Fundamentals for the full life of one instruction.

3. Overlap — why the counter is never idle

Here is the whole point of pipelining. Instead of finishing instruction 1 completely before starting instruction 2, we start instruction 2 the moment instruction 1 vacates the first station.

Read the diagram down a column. Each vertical column is one clock cycle $t$. Look at cycle 4 in the figure: instruction I1 sits in MEM while instruction I4 sits in IF. Both want memory on the same tick. That is the structural hazard, made of parts you now fully own: a clock tick, two instructions, two stages, one shared resource.

Why the topic needs it. Overlap is what makes pipelines fast — but overlap is also exactly what forces two instructions to grab the same tool at the same time. No overlap, no structural hazard. This is why the parent note opens with "different instructions occupy different stages at the same time."

4. Resource — the shared tool

The picture: a single shared bathroom (from the parent's analogy) is a resource. So is one kitchen oven, one calculator, one doorway.

Why "single instance" matters. Building two of a resource costs silicon area and power. Designers often build one copy of an expensive resource. If two stages need that one copy on the same tick → collision. This is the root of every structural hazard.

Two resources you must specifically know:

• The ALU (Arithmetic Logic Unit): the block that does $+,-$, comparisons, etc. It normally lives in the EX stage.
• The register file: a tiny table of numbered storage boxes. It has a limited number of ports — doorways for reading and writing. A standard file has 2 read ports + 1 write port, meaning it can serve at most two reads and one write per clock tick. Ask for a third read → collision.

5. Stall — the fix, and its cost

The picture: the person waiting for the bathroom just stands still for one drumbeat. Everyone behind them waits too. One beat of the whole line is wasted.

Why the topic needs it. The stall is the consequence of the hazard. Every structural hazard is resolved either by adding hardware (so no waiting) or by stalling (so we accept the wait). See Pipeline Stalls for the general mechanism.

6. The one bit of math — CPI

Everything above is pictures. Now the single number that measures how much a hazard hurts.

Why this ratio and not something else? Because performance is "how many instructions per beat," and CPI is exactly the inverse of that — it directly answers "how many drumbeats did each instruction cost me on average?" A perfect pipeline finishes one instruction every beat, so ideal $\text{CPI}=1.0$.

Every stall adds one wasted beat. If a fraction $p$ of instructions each suffer $s$ stall cycles, then:

Read it in words. Start from one beat per instruction ($1$), then add the extra beats you were forced to waste ($p\times s$). Nothing more.

Prerequisite map

Read top to bottom: ticks and instructions build stages; stages overlapping plus a shared resource create the hazard; the hazard forces a stall; stalls raise CPI; higher CPI means lost performance. This same chain underlies its cousins Data Hazards and Control Hazards.

Equipment checklist

Test yourself — cover the right side and answer aloud.

Next, apply all of this to the concrete collisions in the parent topic, and see how it contrasts with Instruction-Level Parallelism and Superscalar Processors where extra ports are added to dissolve these hazards.