Foundations — Structural hazards

5.2.5 · D1 · Hardware › Processor Datapath & Pipelining › Structural hazards

Isse pehle ki aap samjho kyun do instructions hardware ke liye clash karti hain, aapko us sentence ka har word apna banana hoga: "pipeline" kya hoti hai, "stage" kya hota hai, "clock cycle" kya hota hai, "resource" kya hota hai, aur thodi si arithmetic (CPI) jo nuksan naapti hai. Hum sab kuch zero se banate hain.

1. Clock cycle — dil ki dhadkan

Tasveer: socho ek drummer steady beat kar raha hai. Har beat par, saare dancers ek position aage badhte hain. Koi beats ke beech mein nahi hilta. Processor bhi waisa hi hai — kaam sirf beat par "count" hota hai.

Topic ko iska kyun zaroorat hai. Ek structural hazard define hota hai do cheezein "ek hi clock cycle mein" hone ke roop mein. Agar aap ek discrete tick imagine nahi kar sakte, toh aap do instructions ko ek hi tick par aate nahi dekh sakte. Parent note mein "simultaneous" ka matlab literally hai "is drum ki ek hi beat par."

Hum ek specific cycle ko $t=1,2,3,\dots$ likhenge — bas beats count karte hue. Symbol $t$ yahan sirf yahi matlab rakhta hai: hum kis beat par hain.

2. Instruction aur uske paanch stages

Ek instruction ko poori tarah run karne ke liye, classic design kaam ko paanch steps mein todta hai, jise stages kehte hain. Socho ek paanch-station counter par sandwich banana:

Tasveer: ek line mein paanch stations. Ek instruction IF par enter hoti hai aur left-to-right chalti hai, ek station pratihar clock cycle (wahan phir humara drumbeat aaya).

Topic ko iska kyun zaroorat hai. Inme se do stages — IF aur MEM — dono memory mein jaate hain. Yeh baat yaad rakho; yahi sabse common structural hazard hai, aur jab tak aap un do stages ko naam nahi de sakte jo isko cause karti hain, tab tak collision nahi dekh sakte. Ek instruction ki poori zindagi ke liye Pipelining Fundamentals dekho.

3. Overlap — counter kyun kabhi idle nahi hota

Pipelining ka poora point yahi hai. Instruction 1 ko poori tarah khatam karne ke baad Instruction 2 shuru karne ki jagah, hum Instruction 2 tab shuru karte hain jab Instruction 1 pehla station khali kare.

Diagram mein column neeche padhein. Har vertical column ek clock cycle $t$ hai. Cycle 4 dekho figure mein: instruction I1 MEM mein baitha hai jabki instruction I4 IF mein baitha hai. Dono memory chahte hain ek hi tick par. Yahi structural hazard hai, un parts se milkaar bana jo ab aapke paas hain: ek clock tick, do instructions, do stages, ek shared resource.

Topic ko iska kyun zaroorat hai. Overlap hi pipelines ko fast banata hai — lekin overlap hi yahi force karta hai ki do instructions ek hi tool ko ek saath pakad lein. Koi overlap nahi, koi structural hazard nahi. Isliye parent note "different instructions occupy different stages at the same time" se shuru hota hai.

4. Resource — shared tool

Tasveer: ek shared bathroom (parent ki analogy se) ek resource hai. Ek kitchen oven bhi, ek calculator bhi, ek doorway bhi.

"Single instance" kyun matter karta hai. Ek resource ki do copies banana silicon area aur power leta hai. Designers aksar ek mahenga resource ek hi copy banaate hain. Agar do stages ek hi copy ko ek hi tick par chahein → collision. Har structural hazard ki yahi jad hai.

Do resources jo specifically jaanne chahiye:

• ALU (Arithmetic Logic Unit): woh block jo $+,-$, comparisons, etc. karta hai. Yeh normally EX stage mein rehta hai.
• Register file: numbered storage boxes ki ek choti table. Iske limited ports hain — padhne aur likhne ke liye doorways. Ek standard file mein 2 read ports + 1 write port hote hain, matlab yeh ek clock tick mein zyada se zyada do reads aur ek write serve kar sakti hai. Teesra read maango → collision.

5. Stall — fix, aur uski cost

Tasveer: bathroom ke liye wait kar raha insaan bas ek drumbeat ke liye khada rehta hai. Uske peeche sab bhi wait karte hain. Poori line ka ek beat waste ho jaata hai.

Topic ko iska kyun zaroorat hai. Stall hazard ka consequence hai. Har structural hazard ya toh hardware add karke (taaki koi wait nahi) ya stalling se (taaki hum wait accept karein) resolve hota hai. General mechanism ke liye Pipeline Stalls dekho.

6. Thodi si math — CPI

Upar sab kuch tasveerein hain. Ab ek number jo maapti hai ki hazard kitna hurt karta hai.

Yeh ratio kyun aur koi cheez kyun nahi? Kyunki performance hai "har beat kitni instructions," aur CPI bilkul uska ulta hai — yeh directly jawaab deta hai "ek instruction ne mujhe average mein kitne drumbeats liye?" Ek perfect pipeline har beat ek instruction khatam karta hai, toh ideal $\text{CPI}=1.0$.

Har stall ek wasted beat add karta hai. Agar $p$ fraction instructions mein se har ek $s$ stall cycles suffer kare, toh:

Words mein padho. Ek beat per instruction ($1$) se shuru karo, phir jod do woh extra beats jo waste karne par majboor kiye gaye ($p\times s$). Bas itna hi.

Prerequisite map

Upar se neeche padho: ticks aur instructions stages banate hain; stages overlap hona plus ek shared resource hazard create karta hai; hazard stall force karta hai; stalls CPI badhate hain; zyada CPI matlab lost performance. Yahi chain iske cousins Data Hazards aur Control Hazards ke neeche bhi hai.

Equipment checklist

Khud test karo — right side cover karo aur zaur se jawaab do.

Yeh sab parent topic mein concrete collisions par apply karo, aur dekho yeh Instruction-Level Parallelism aur Superscalar Processors se kaise contrast karta hai jahan extra ports add karke in hazards ko khatam kiya jaata hai.