Multi-cycle datapath — Hinglish notes

5.2.2 · Hardware › Processor Datapath & Pipelining

Multi-cycle exist kyun karta hai?

Yeh bura kyun hai? add ko koi memory access nahi chahiye lekin phir bhi iske liye charge hoti hai. Clock "ek size sabke liye — sabse slow size" wali hoti hai.

Fix kya hai? Execution ko balanced sub-steps mein todo (har step ≈ ek functional-unit delay). Ab clock sirf ek step ke liye kaafi lambi honi chahiye, poori instruction ke liye nahi: $T_{m u l t i} = max (delay of a single step) ≪ T_{s in g l e}$

Hum hardware reuse kaise karte hain? Kyunki steps alag-alag cycles mein hote hain, ek ALU / ek memory kai roles serve kar sakti hai. Isliye hum:

Instructions aur data dono ke liye ek single memory use karte hain (alag-alag cycles mein access hoti hai).
PC increment, branch target, aur arithmetic ke liye ek single ALU use karte hain.
Internal registers (IR, A, B, ALUOut, MDR) add karte hain jo cycles ke beech values hold karte hain, kyunki combinational signals clock edge par gum ho jaate hain.

Paanch canonical steps

Har instruction paanch steps use nahi karti. Har type ke liye cycle count:

Instruction	Steps used	# Cycles
R-type (`add`)	IF ID EX WB	4
`lw`	IF ID EX MEM WB	5
`sw`	IF ID EX MEM	4
`beq`	IF ID EX	3
`j`	IF ID EX	3

(Jump ko EX tak pahunchna padta hai kyunki PC step 3 mein update hota hai — jump uses IF, ID, EX = 3 cycles.)

Har step ko first principles se derive karna

Hum derive karte hain kya kaam hona chahiye har cycle mein, aur kaun sa internal register result ko pakadta hai.

Step 1 — IF (Instruction Fetch)

Hume instruction bits chahiye, isliye address PC par memory read karo.
Hum PC+4 bhi ready chahte hain (default next instruction). $IR \leftarrow Memory [PC], PC \leftarrow PC + 4$ IR mein latch kyun karo? Kyunki agli cycle mein Memory data ke liye use ho sakti hai — instruction bits otherwise kho jaate. PC+4 abhi kyun compute karo? ALU is cycle mein free hai, isliye hum ise PC increment ke liye reuse karte hain.

Step 2 — ID (Decode / Register Fetch)

Hume abhi instruction type nahi pata, isliye woh kaam karo jo sab possibilities ke liye useful ho: $A \leftarrow Reg [IR [25 : 21]], B \leftarrow Reg [IR [20 : 16]]$ $ALUOut \leftarrow PC + (sign-ext (IR [15 : 0]) ≪ 2)$ Branch target speculatively kyun compute karo? ALU idle hai; agar instruction beq nikli toh target already hamare paas hai — koi extra cycle waste nahi hoga. Yeh optimistic pre-computation hai.

Step 3 — EX (type ke hisaab se)

R-type: $ALUOut \leftarrow A op B$
lw/sw: $ALUOut \leftarrow A + sign-ext (IR [15 : 0])$ (effective address)
beq: agar $A = B$ toh $PC \leftarrow ALUOut$ (step 2 ka target)
jump: $PC \leftarrow {PC [31 : 28], IR [25 : 0], 00}$ (PC yahan update hota hai — isliye j ko EX step chahiye)

Step 4 — MEM

lw: $MDR \leftarrow Memory [ALUOut]$
sw: $Memory [ALUOut] \leftarrow B$ — aur sw yahan khatam ho jaata hai.
(R-type memory touch nahi karta; yeh step skip kar deta hai aur Step 5 mein write back karta hai.)

Step 5 — WB

lw: $Reg [IR [20 : 16]] \leftarrow MDR$
R-type: $Reg [IR [15 : 11]] \leftarrow ALUOut$ — R-type yahan finish hoti hai (EX mein compute kiya gaya ALU result write back karta hai).

Worked examples

Common mistakes (Steel-manned)

Flashcards

Single-cycle clock period sabse dheemi instruction ki delay ke barabar kyun honi chahiye?

Kyunki har instruction exactly ek cycle mein complete hoti hai, cycle worst-case path ke liye kaafi lambi honi chahiye (lw).

Multi-cycle vs single-cycle ka core trade-off kya hai?

Instruction ke liye zyada cycles, lekin bahut chota clock period, plus hardware reuse (ek ALU, ek memory).

Paanch multi-cycle steps ke naam order mein batao.

IF, ID, EX, MEM, WB.

Internal registers (IR, A, B, ALUOut, MDR) kyun chahiye?

Clock edges ke across combinational results hold karne ke liye taaki baad wala cycle pehle wale cycle ki value use kar sake.

R-type instruction kitne cycles leti hai aur kis step mein write back karti hai?

4 cycles — IF, ID, EX, WB; yeh MEM skip karti hai aur WB step mein ALUOut ko register file mein likhti hai.

Jump instruction ko EX step kyun chahiye (3 cycles, 2 nahi)?

Kyunki PC step 3 (EX) mein update hota hai; naya target address wahan PC mein likha jaata hai.

Multi-cycle ek single unified memory kyun use kar sakta hai?

Instruction fetch aur data access alag cycles mein hote hain, isliye simultaneous access ki zaroorat nahi.

Branch target ID step mein kyun compute kiya jaata hai?

ALU tab idle hota hai; ise speculatively pre-compute karna ek cycle bachata hai agar instruction branch nikle.

IF ke dauran ALU kya compute karta hai?

PC + 4 (default next instruction address).

Kaun sa stage aksar multi-cycle clock period set karta hai, aur kyun?

ID — yeh usi cycle mein register-file read (100 ps) ke baad ALU branch-target calc (200 ps) karta hai = 300 ps.

Average CPI ka formula?

CPI = Σ fᵢ·cᵢ (frequency × cycle count instruction types par sum kiya gaya).

lw write-back se pehle data kis step aur register mein rakhta hai?

MEM step mein, MDR (Memory Data Register) mein.

Recall Feynman: ek 12-saal ke bachche ko explain karo

Socho LEGO model banana. Single-cycle = poora model ek giant timed block mein banana padta hai, aur timer sabse mushkil model ke liye set hai, isliye easy models mein time waste hota hai. Multi-cycle = chhote steps mein banao (pieces dhundo, base snap karo, upar add karo...). Har step quick hai, aur ek easy model bas kam steps karta hai aur jaldi ruk jaata hai. Tum same table (memory) aur same haath (ALU) alag steps par reuse karte ho, isliye kam equipment chahiye. Tum zyada chhote steps karte ho, lekin har ek fast hai — aur jo parts tumhe nahi chahiye unpar koi effort waste nahi hota.

Connections

Single-cycle datapath — woh baseline jise yeh improve karta hai
Pipelining — multi-cycle idea ko aage le jaata hai: alag instructions ke steps overlap karta hai
Control unit — FSM vs microprogramming — multi-cycle ko finite-state control chahiye (har step ke liye ek state)
CPI and CPU performance equation — cycles × period execution time kaise deta hai
ALU design — shared unit jo IF/ID/EX mein reuse hoti hai
Memory hierarchy — ek unified memory port real constraint kyun hai