Instruction-level semantics and exceptions: Exercises

5.1.12 · D4 · Hardware › Instruction Set Architecture (ISA) › Instruction-level semantics and exceptions

Shuru karne se pehle, do facts ka ek chhota recap jinka hum sabse zyada use karenge:

Recall Do facts jo tum baar baar use karoge

Fault return PC ::: wahi instruction (usse restart karo) Trap return PC ::: agla instruction (usne apna kaam kar diya)

Hum yeh bhi assume karte hain, jab tak problem kuch aur na kahe, ki fixed-length ISA of 4 bytes per instruction hai, toh default next instruction hamesha $P C + 4$ hota hai. Addresses hex mein likhe jaate hain jaise $0 x 400$ .

Ek symbol jo hum neeche lagbhag har solution mein use karenge, uski apni plain-words definition pehle deni zaroori hai:

Level 1 — Recognition

(Kya tum cheez ko naam de sakte ho aur sahi box pick kar sakte ho?)

Exercise 1.1 — Har event ko classify karo

Neeche diye gaye har event ke liye batao ki woh Fault, Trap, Abort, ya Interrupt hai:

Ek syscall instruction jo file read ke liye request kar rahi hai.
Ek LW (load word) jo aisi page touch kar raha hai jo physical memory mein nahi hai.
Keyboard ka ek key press hona jab tumhara program arithmetic kar raha ho.
Memory controller ek uncorrectable multi-bit error report kar raha hai.
Ek division DIV R1, R2, R3 jahan $R 3 = 0$ hai.

Recall Solution

Trap — deliberate, program ne khud service maangi; uske baad resume karo.
Fault — correctable, load write karne se pehle detect hua; wahi load dubara chalaao.
Interrupt — external device, asynchronous, current arithmetic se koi matlab nahi.
Abort — unrecoverable hardware error; program continue nahi kar sakta.
Fault — commit se pehle detect hua; div-by-zero OS ke liye correctable hai (jaise ek handler ko signal karna), aur yeh synchronous hai (same inputs isse reproduce karte hain).

Exercise 1.2 — Architectural ya microarchitectural?

Har piece of machine state ko Architectural (visible, ISA ke dwara define) ya Microarchitectural (invisible implementation detail) label karo: General-purpose register R4; branch predictor ka history table; program counter PC; reorder buffer; ek data cache line; carry flag.

Recall Solution

R4 — Architectural (programmer-visible register).
Branch predictor table — Microarchitectural (pure speed hint, koi ISA meaning nahi).
PC — Architectural (har instruction ki semantics ke dwara define).
Reorder buffer — Microarchitectural (in-order commit ke liye bookkeeping).
Data cache line — Microarchitectural (memory ki ek copy; ISA memory define karta hai, cache nahi).
Carry flag — Architectural (ek status flag jo ISA specify karta hai).

Test: Kya Intel ise hata ya redesign kar sakta hai bina tumhara compiled program tod ke? Agar haan → microarchitectural. Agar nahi → architectural. Dekho ISA as a Hardware–Software Contract.

Level 2 — Application

(State-transition aur return-PC rules mein plug karo.)

Exercise 2.1 — ADD semantics apply karo

Pehle: $R 2 = 10$ , $R 3 = 7$ , $P C = 0 x 1000$ . ADD R1, R2, R3 execute karo. Naya $R 1$ aur naya $P C$ do.

Recall Solution

Semantics hai $R 1 \leftarrow R 2 + R 3, P C \leftarrow P C + 4$ .

$R 1 = 10 + 7 = 17$ .
$P C = 0 x 1000 + 4 = 0 x 1004$ .

PC update instruction ke meaning ka hissa hai — ek instruction jo compute kare lekin PC advance karna bhool jaaye woh hamesha ke liye execute hota rahega.

Exercise 2.2 — Branch semantics apply karo

BEQ R1, R2, offset $P C = 0 x 2000$ par hai. Yahan offset instructions count karta hai (har 4 bytes), toh taken target hai $P C + 4 + 4 \cdot offset$ . Next PC compute karo jab: (a) $R 1 = R 2 = 5$ aur $offset = 3$ ; (b) $R 1 = 5, R 2 = 9$ , $offset = 3$ .

Recall Solution

$P C \leftarrow {P C + 4 + 4 \cdot offset P C + 4 R 1 = R 2 otherwise$ (a) Equal ⇒ taken: $0 x 2000 + 4 + 4 \cdot 3 = 0 x 2000 + 16 = 0 x 2010$ . (b) Not equal ⇒ fall through: $0 x 2000 + 4 = 0 x 2004$ .

Gaur karo ki ADD ke mukable ek branch sirf PC-write rule badalta hai — wahi read/compute skeleton, alag step 4. Dekho Pipelining and Hazards yeh jaanne ke liye ki branches kyun expensive hain.

Exercise 2.3 — Trap ke liye return PC

Ek syscall $0 x 8040$ par hai (4-byte instructions). Handler return karne ke liye kaunsa EPC use karta hai, aur kyun?

Recall Solution

syscall ek trap hai: usne apna meaning pehle se perform kar liya hai (usne OS request lodge kar di). Hum agla instruction resume karte hain, toh $E P C = 0 x 8040 + 4 = 0 x 8044$ . $0 x 8040$ par return karna wahi request dobara issue kar dega. Dekho System Calls and Privilege Levels.

Exercise 2.4 — Fault ke liye return PC

$0 x 8060$ par ek LW R5, 0(R6) page-fault karta hai. Handler kaunsa EPC use karta hai, aur jab handler start hota hai tab $R 5$ ki value kya hai?

Recall Solution

Page fault ek fault hai: yeh load commit hone se pehle detect hota hai, toh $R 5$ unchanged hai (precise-exception rule 2). $E P C = 0 x 8060$ — LW khud ka address — kyunki OS page laane ke baad, wahi load dubara run hona chahiye taaki actual data deliver ho sake. Dekho Virtual Memory and Page Faults.

Level 3 — Analysis

(Ordering, precision, aur kaunsa event jeetega — is par reason karo.)

Exercise 3.1 — Kaunsa exception report hoga?

Program order mein $I_{1}, I_{2}, I_{3}, I_{4}$ . Ek cycle mein ek wide out-of-order machine detect karta hai: $I_{2}$ mein div-by-zero fault hai, aur $I_{4}$ mein page fault hai. Kaunsa exception report hoga, aur jab handler start ho tab baaki teen instructions ke baare mein kya sach hona chahiye?

Recall Solution

Program order mein sabse purani faulting instruction report karo ⇒ $I_{2}$ (div-by-zero).

$I_{1}$ fully committed hona chahiye (yeh reported fault se purana hai ⇒ precise rule 1).
$I_{2}$ aur usse naye ( $I_{3}, I_{4}$ ) ne architectural state modify nahi ki honi chahiye (rule 2).
$I_{4}$ ka page fault discard ho jaata hai — clean sequential world mein execution kabhi $I_{4}$ tak pahunchi hi nahi, kyunki woh $I_{2}$ par ruk jaani chahiye thi. Agar OS $I_{2}$ dobara run karta hai aur fix ke baad bhi fault aata hai, tabhi $I_{4}$ ka mauka aayega. Dekho Out-of-Order Execution and the Reorder Buffer.

Exercise 3.2 — Precision kahan se aati hai?

Ek out-of-order CPU physically instructions galat order mein execute karta hai. Ek paragraph mein explain karo ki architectural state har exception par precise kaise ho sakti hai. Zimmedaar stage ka naam lo.

Recall Solution

Instructions compute out of order ho sakte hain, lekin woh commit (retire) karte hain — architecturally visible bante hain — strictly program order mein, commit/retire stage par jo reorder buffer se fed hai. Kisi naye instruction ka result buffer mein baitha rehta hai, invisible, jab tak har purana instruction retire na ho jaaye. Jab fault detect hota hai, hardware faulting instruction aur usse naye sab ko squash kar deta hai (unke buffered results phank diye jaate hain) aur purane waalon ko retire karne deta hai. Toh visible state hamesha bilkul clean sequential state hoti hai kisi instruction boundary par.

Exercise 3.3 — Synchronous vs asynchronous, re-running se test karo

Tum ek program do baar identical input ke saath run karte ho. Pehle run mein instruction #500 par page fault aata hai aur instruction #900 ke aaspaas kahin timer interrupt aata hai. Dono mein se kaunsa doosre run mein exact same instruction par hone ki guarantee hai? Kyun?

Recall Solution

Page fault ki guarantee identical hogi: exceptions synchronous hote hain — instruction stream aur data ka deterministic function, toh same inputs use #500 par har baar reproduce karte hain. Timer interrupt asynchronous hai — external wall-clock timing se driven, program se nahi. Doosre run mein woh kisi alag instruction par land kar sakta hai, ya us window mein fire hi na kare. Dekho Interrupts and I/O.

Level 4 — Synthesis

(Multiple rules ko ek poore scenario mein combine karo.)

Exercise 4.1 — Full page-fault timeline

Memory mein, program order mein 4-byte spacing par:

Addr	Instr
$0 x 300$	`ADD R1, R2, R3`
$0 x 304$	`LW R5, 0(R6)` (page not present)
$0 x 308$	`SUB R7, R1, R5`

Poora event sequence walk karo: kaunsi instructions commit hoti hain, kaunsa EPC save hota hai, OS kya karta hai, aur execution kahan resume hoti hai. Assume karo ki fault precise hai.

Recall Solution

Neeche ki figure wahi teen-row timeline draw karti hai jo yahaan words mein describe hai — pehle text padho, phir picture se check karo.

Figure — Instruction-level semantics and exceptions

$0 x 300$ ADD commits. Yeh fault se purana hai, toh $R 1$ fully update karta hai. (Top row, chalk blue mein — "commits (older)".)
$0 x 304$ LW faults. Page absent hai. Commit se pehle detect hua ⇒ $R 5$ nahi likha jaata. (Middle row, chalk pink — "FAULT (page absent)".)
$0 x 308$ SUB squash ho jaata hai. Yeh fault se newer hai; chahe usne speculatively kuch compute kar liya ho, woh result discard ho jaata hai — $R 7$ untouched rehta hai. (Bottom row, plain chalk — "squashed (younger)".) Achha hi hua: yeh $R 5$ par depend karta hai, jise fault ne stale chhod diya.
State save karo. $E P C = 0 x 304$ (LW ka apna address, kyunki yeh fault hai), plus cause aur faulting virtual address. (Figure mein pale-yellow curved arrow saved state se $0 x 304$ ki taraf point karti hai.)
OS handler run karta hai. Woh missing page ko physical memory mein laata hai (dekho Virtual Memory and Page Faults), page table update karta hai, aur $E P C$ par return karta hai.
$0 x 304$ par resume. LW dobara execute hota hai, is baar present page milti hai, $R 5$ likhta hai, aur execution normally SUB par $0 x 308$ par flow karti hai.

Net effect: program ko kuch notice nahi hota siwaaye ek time delay ke — promise "execute in order, completely" poori tarah rakhi jaati hai.

Exercise 4.2 — Trap timeline with a return value

$0 x 500$ par ek syscall current time request karta hai; OS result $R 2$ mein likhta hai aur return karta hai. Call se pehle $R 2 = 0$ , $P C = 0 x 500$ . Successful return ke baad, $R 2$ (conceptually) aur PC do.

Recall Solution

syscall ek trap hai ⇒ agla instruction resume karo: $P C = 0 x 500 + 4 = 0 x 504$ .
OS ne requested kaam kar diya aur deliberately architectural register $R 2$ mein result likha (yeh trap ka "apna meaning complete karna" hai). Toh $R 2$ ab woh time value hold karta hai jo OS ne diya.
Fault se contrast karo: ek fault handler faulting register mein return value nahi chodta — woh environment fix karta hai aur wahi instruction dobara run karata hai, jo phir khud value produce karta hai.

Level 5 — Mastery

(Design-level judgement aur edge cases.)

Exercise 5.1 — Simultaneous events mein priority

Ek cycle mein: instruction $I_{2}$ fault raise karta hai, aur ek timer interrupt bhi pending ho jaata hai. Dono purani instructions $I_{0}, I_{1}$ commit ho chuki hain. Ek defensible policy batao ki kya hoga, aur synchronous/asynchronous distinction use karke justify karo.

Recall Solution

Ek clean, defensible policy: pehle synchronous exception ki instruction boundary resolve karo, phir interrupt lo. Concretely — $I_{2}$ aur younger ko squash karo, fault ke liye $E P C =$ $I_{2}$ ka address save karo, aur fault handler lo. Interrupt asynchronous hai: yeh kisi particular instruction se tied nahi, toh isse thoda baad service karna theek hai (kai designs ise agle clean commit boundary par lete hain, jo fault handling ne abhi create ki). Key correctness rule: jo bhi lein, saved EPC ko ek precise instruction boundary par point karna chahiye taaki dono handlers cleanly return kar sakein. (Real ISAs ek exact priority table specify karte hain; principle — precision dono taraf preserved — wahi matter karta hai.)

Exercise 5.2 — Degenerate / zero cases

Har edge case ka jawab do aur ek-line reason do:

Ek instruction jo same register read aur write karta hai, ADD R1, R1, R1, $R 1 = 6$ ke saath. Final $R 1$ ?
offset = 0 wala branch. Taken branch kahan jaata hai?
Address $0 x 700$ par ek syscall jo ek unmapped page se pehle bilkul aakhri instruction hai — yani agla address $0 x 704$ aisi page mein hai jo memory mein present nahi. Trap kaunsa EPC save karta hai, aur execution return hone par turant kya hota hai?

Recall Solution

$R 1 = 12$ . Semantics per instruction atomic hain: dono source operands ka read purani value par hota hai ( $6$ ), write baad mein hota hai ( $6 + 6 = 12$ ). Sequential model write ko is instruction ke apne read mein feed back hone se forbid karta hai.
Taken target $= P C + 4 + 4 \cdot 0 = P C + 4$ — fall through ke same address par. Ek offset-0 taken branch simply agle instruction par land karta hai; yeh legal lekin pointless jump hai.
$E P C = 0 x 700 + 4 = 0 x 704$ (yeh trap hai, next par resume karo). Return par PC unmapped page mein point karta hai, toh $0 x 704$ par instruction fetch karna khud page-fault karta hai. Yeh ek alag, baad ka fault hai — instruction-fetch page fault — bilkul apne aap handle hoga. Trap ka return phir bhi sahi tha; machine ne bas ek fresh, distinct exception turant raise kar di. Do alag events, har ek apni precise boundary par, ek ek karke resolve hote hain.

Exercise 5.3 — Contract kyun matter karta hai

Do sentences mein explain karo ki sequential-execution promise kaise ek chip vendor ko radically faster CPU ship karne deta hai jo tumhara purana unmodified binary correctly run kare.

Recall Solution

Software sirf is baat par depend karta hai ki architectural state aise behave kare jaise instructions ek-ek karke order mein run hue hों; ISA exactly yahi guarantee karta hai. Toh vendor sab microarchitecture redesign kar sakta hai — deeper pipelines, out-of-order execution, speculation — aur jab tak commit in-order rahe aur exceptions precise rahein, tumhara purana binary wahi identical visible results dekhega, bas faster. Yahi to poora point hai ISA as a Hardware–Software Contract ka.

Recall Final self-check (ek line each)

Fault return PC vs trap return PC ::: fault → same instruction; trap → next instruction Kai exceptions mein se kaunsa report hoga ::: program order mein sabse purana Out-of-order CPU mein precise exceptions kya enforce karta hai ::: in-order commit/retire (reorder buffer) Synchronous vs asynchronous ::: exception = instruction stream se caused; interrupt = external timing ADD R1, R1, R1 with R1=6 ::: 12 (read-before-write, atomic) EPC kya hold karta hai ::: woh return address jo exception fire hone par bookmark hota hai