Load - store architecture model — Hinglish notes

5.1.9 · Hardware › Instruction Set Architecture (ISA)

Load/store architecture kya hai?

YEH DESIGN KYO? Teen key reasons:

Uniform instruction timing: Memory access unpredictable hoti hai (cache hits/misses). Isse alag karne se non-memory instructions fast aur predictable ban jaati hain.
Simplified hardware: ALU ko memory interface logic ki zaroorat nahi. Decode simpler hoti hai (fewer instruction formats).
Compiler optimization: Explicit data movement register allocation aur instruction scheduling ko optimize karna aasaan banata hai.

Alternative: Register-memory architectures

x86 se contrast (ek register-memory architecture):

; x86 yeh kar sakta hai:
ADD [memory_addr], EAX    ; Read memory, add EAX, write back
 
; RISC load/store require karta hai:
LDR R1, [memory_addr]     ; Load into register
ADD R1, R1, R2            ; Operate on registers
STR R1, [memory_addr]     ; Store back

x86 "better" kyun lagta hai: Fewer instructions! Lekin x86 ka ADD complexity hide karta hai—yeh actually internally 3 operations kar raha hai, aur iska timing cache behavior ke basis par wildly vary karta hai.

RISC actually better kyun hai:

Har instruction ek kaam karta hai → pipelining aasaan hai
Predictable timing → real-time deadlines meet karna aasaan
Simpler decode → kam power, higher clock speeds

Performance advantage derive karna

First principles se shuru karte hain:

Execution time = (Number of instructions) × (Cycles per instruction) × (Clock period) $T = I \times CPI \times T_{clk}$
CPI alag kyun hoti hai?
- Register-memory: Har instruction memory ka wait karke stall ho sakti hai (variable latency)
- Load/store: Memory ops explicit aur isolated hoti hain, isliye pipeline ko exactly pata hota hai kab stall karna hai
Example scenario: Memory se do numbers add karna x86 (register-memory):
```
ADD [0x1000], EAX  ; ~10 cycles if cache miss
```
ARM (load/store):
```
LDR R1, [R0]      ; ~10 cycles if cache miss
ADD R1, R1, R2    ; ~1 cycle (register op)
STR R1, [R0]      ; ~10 cycles if cache miss
```
ARM mein 3 instructions hain vs. 1, lekin:
- ARM loads/stores hone ke dauran ADD ko pipeline kar sakta hai
- ARM independent loads ko reorder kar sakta hai (out-of-order execution aasaan)
- ARM ka simple decoder 3 GHz par chalta hai vs. x86 ka 2.5 GHz (example numbers)
Average CPI nikalna (yeh "4" kahan se aaya?): Do memory ops mein se har ek miss par ~10 cycles lagti hai, ALU op ~1 cycle. Lekin woh numbers per-instruction latencies hain, throughput CPI nahi. Kyunki ek pipelined machine yeh instructions overlap karti hai, effective per-instruction cost bahut kam hoti hai. Aaiye explicitly compute karte hain.

Maano steady-state pipelining mein, ek cache miss pipe ko stall karta hai lekin baad ki independent instructions issue hoti rehti hain. Ek common textbook approximation hai: $CPI_{avg} = \frac{total pipeline cycles}{number of instructions}$

Maano 3-instruction ARM sequence, overlap ke saath, 12 pipeline cycles total mein complete hoti hai (ek memory miss largely doosre kaam ke peechhe chupi hai, plus base pipeline fill): $CPI_{ARM} = \frac{12}{3} = 4 cycles/instruction$

x86 ke liye, single fused instruction apni internal read-modify-write ko overlap nahi kar sakti, isliye iska per-instruction cost poore ~10-cycle latency par rehta hai: $CPI_{x86} = \frac{10}{1} = 10 cycles/instruction$

Isliye load/store ka low CPI (4) register-memory ke high CPI (10) ko haraata hai, zyada instructions hone ke bawajood.
Net result: $T_{x86} = 1 \times 10 \times 0.4 ns = 4.0 ns$ $T_{ARM} = 3 \times 4 \times 0.33 ns = 4.0 ns$

(Simplified hai, lekin trade-off dikhata hai. Practice mein, ARM aksar better pipelining ki wajah se jeetta hai.)

Worked example Example 1: Simple array sum (MIPS-style)

Task: Do array elements sum karo: c = a[i] + b[i]

# Assume R1 = &a[i], R2 = &b[i], R3 = &c[i]
LW   R4, 0(R1)      # Load a[i] into R4
LW   R5, 0(R2)      # Load b[i] into R5
ADD  R6, R4, R5     # R6 = R4 + R5
SW   R6, 0(R3)      # Store R6 to c[i]

Yeh step kyun?

LW (load word): Memory → Register hi ek maatra tarika hai data CPU mein laane ka
ADD: ALU sirf registers dekh sakta hai, kabhi memory nahi
SW (store word): Results explicitly wapas likhne padte hain

x86 se contrast:

MOV EAX, [a+i]      ; Load and operate...
ADD EAX, [b+i]      ; ...ek hi instruction mein ho sakta hai
MOV [c+i], EAX

x86 mein 3 instructions hain, MIPS mein 4. Lekin MIPS instructions simpler hain → faster clock, easier pipeline.

Worked example Example 2: Register pressure scenario

Task: d = (a + b) * (c + 3)

Load/store (ARM-style):

LDR  R1, [R10]      # Load a
LDR  R2, [R11]      # Load b
ADD  R3, R1, R2     # R3 = a + b
LDR  R4, [R12]      # Load c
ADD  R5, R4, #3     # R5 = c + 3 (immediate)
MUL  R6, R3, R5     # R6 = R3 * R5
STR  R6, [R13]      # Store d

Yeh step kyun?

Intermediate results (a+b), (c+3) operations ke beech registers mein rehte hain
Isliye load/store architectures mein bahut saare registers hote hain (MIPS/RISC-V mein 32 vs. 32-bit x86 mein 8)
Zyada registers → kam register spilling to memory Register-memory alternative:

MOV  EAX, [a]
ADD  EAX, [b]        ; Result in EAX
MOV  EBX, [c]
ADD  EBX, 3
IMUL EAX, EBX        ; two-operand register multiply (MUL ka 2-operand form nahi hai)
MOV  [d], EAX

Kam registers chahiye, lekin variable-latency instructions pipeline ko complicated banate hain.

IMUL vs MUL par note: x86 ka MUL ek one-operand instruction hai jo implicitly EAX use karta hai aur result EDX:EAX mein likhta hai. Do arbitrary registers ko ek single register mein multiply karne ke liye (EAX = EAX * EBX), aapko IMUL EAX, EBX use karna padta hai, jiska two-operand form hota hai.

Common mistake Mistake: "Load/store slower hai kyunki zyada instructions hain"

Yeh sahi kyun lagta hai: 4 instructions > 1 instruction, toh zyada time lagna chahiye!

Steel-man argument: Agar instructions free hote, toh yeh sach hota. Ek single complex instruction jo load+add+store kare chahiye teen alag instructions se behtar ho.

Yeh galat kyun hai:

Instructions free nahi hain: Complex instructions mein longer decode times, variable latencies hoti hain
Clock speed trade-off: Simple instructions → shorter critical path → higher frequency
Pipelining: Load/store kaam ko un stages mein split karta hai jo overlap hoti hain (pipeline parallelism)
Modern CPUs: Out-of-order execution simple, explicit dependencies ke saath better kaam karta hai

Fix: Time mein socho, instruction count mein nahi. Measure karo: $Performance = \frac{1}{Execution time} = \frac{f _{clk}}{I \times CPI}$

Recall Ek 12-saal ke bachche ko explain karo

Socho tum math homework kar rahe ho. Tumhare paas ek calculator hai (CPU registers) aur ek backpack full of notes (memory).

Load/store architecture = Ek strict teacher kehta hai: "Tum sirf apni desk par rakhi cheezein use kar sakte ho. Agar tumhe backpack se kuch chahiye, pehle bahar nikalo (load). Jab kaam ho jaaye, wapas rakh do (store). Tum backpack mein haath daalkaar math nahi kar sakte!"

Register-memory architecture = Ek relaxed teacher kehta hai: "Backpack se jo chahiye lo aur seedha wahan calculate karo."

Strict teacher ka rule better kyun hai? Kyunki:

Jab sab kuch desk par ho toh tum tez kaam karte ho (registers memory se 100x faster hain)
Tumhe pata hota hai exactly kab tum backpack mein reach kar rahe ho (predictable timing)
Tumhari desk organized rehti hai (simpler hardware)

Trade-off: Tumhe badi desk chahiye (zyada registers) apne saare papers rakhne ke liye!

Load/store architectures ki key characteristics

1. Instruction format regularity

Yeh matter kyun karta hai: Simpler decode logic, faster instruction fetch.

Saari memory instructions ka same format hai: $LOAD/STORE Rdest/Rsrc, [Rbase + offset]$

Saari ALU instructions: $OP Rdest, Rsrc1, Rsrc2/immediate$

x86 se contrast: 1000 se zyada instruction variants, variable length (1-15 bytes), complex addressing modes.

2. Large register files

Kyun? Kyunki memory directly accessible nahi hai, isliye tumhe workspace chahiye.

Architecture	Type	Registers
ARMv7 (32-bit)	Load/store	16 registers R0–R15, lekin sirf R0–R12 truly general-purpose hain (R13=SP, R14=LR, R15=PC special hain)
AArch64 (ARM 64-bit)	Load/store	31 general-purpose (X0–X30)
MIPS	Load/store	32 general-purpose
RISC-V	Load/store	32 general-purpose
x86 (32-bit)	Register-memory	8 general (16 in x86-64)

Register count derive karna:

Maano ek typical loop body use karta hai:

2-3 array pointers (base addresses)
3-4 loop variables (counters, temporaries)
2-3 intermediate calculation results

Minimum zaroorat: ~8-10 registers.

Lekin compiler optimization ke liye, tumhe iska 2-3× chahiye taaki compiler:

Loops unroll kar sake (variables ki parallel copies chahiye)
Frequently-used values iterations ke across "alive" rakhe
"Spilling" se bache (registers ko memory mein wapas likhna)

Isliye: 32 registers = practical sweet spot (zyada hone par encoding bits bahut zyada lag jaati hain). Yahi wajah hai ki newer AArch64 31 GPRs tak jump kiya, jabki older 32-bit ARMv7 ne sirf 16 total (jinmein se ~13 general hain) se kaam chalaya.

3. Explicit memory ordering

Load/store programmers/compilers ko data movement ke baare mein sochne par majboor karta hai:

// C code
x = a[i] + b[i];
y = c[i] + d[i];

Compiler ko generate karna padta hai:

LDR R1, [a, i]    ; Yeh 4 loads
LDR R2, [b, i]    ; compiler dwara
LDR R3, [c, i]    ; optimal cache
LDR R4, [d, i]    ; usage ke liye reorder ho sakte hain!
ADD R5, R1, R2
ADD R6, R3, R4
STR R5, [x]
STR R6, [y]

Ek register-memory ISA mein, ADD [mem], reg mein implicit memory access yeh optimization opportunities hide kar deta hai.

Modern reality: Hybrid approaches

Observation: Pure load/store jeet gaya. Aaj ke almost saare high-performance CPUs load/store hain:

ARM (phones, Apple M-series, servers)
RISC-V (emerging)
MIPS (legacy embedded)
PowerPC (legacy servers)

Lekin: x86 bhi internally convert karta hai! Modern x86 CPUs:

Complex x86 instructions ko simpler micro-ops (μops) mein decode karte hain
Yeh μops load/store style ke hain
RISC-like core par execute hote hain

Toh x86 ko dono duniya ka bura milta hai: complex decode + load/store execution. Isliye mobile mein ARM jeet raha hai (power efficiency).

Connections

RISC vs CISC philosophy: Load/store defining RISC characteristic hai
Instruction pipelining: Simple instructions efficient pipelines enable karte hain
Register allocation: Compilers ko load/store architectures ke liye bahut registers chahiye
Memory hierarchy: Explicit loads/stores cache behavior ko compiler ke liye expose karte hain
Addressing modes: Load/store addressing mode complexity ko limit karta hai
Instruction encoding: Uniform formats opcode space bachate hain

Flashcards

Load/store architecture kya hai? :: Ek ISA jahan sirf load aur store instructions memory access karti hain, aur saari arithmetic/logic operations exclusively registers par kaam karti hain. Isse register-register architecture bhi kaha jaata hai.

Load/store architecture zyada instructions ke bawajood faster kyun hai?

Higher clock frequency (simpler decode) aur lower CPI (predictable pipelining) increased instruction count ko offset karte hain. Performance = I × CPI / f_clock.

Load/store architecture ke teen main benefits kya hain?

1) Uniform instruction timing (memory access isolated hai), 2) Simplified hardware (ALU ko memory interface ki zaroorat nahi), 3) Easier compiler optimization (explicit data movement).

MIPS vs 32-bit x86 mein kitne general-purpose registers hain?

MIPS mein 32 general-purpose registers hain; 32-bit x86 mein 8 hain (x86-64 mein 16). Load/store architectures ko zyada registers chahiye kyunki memory directly accessible nahi hoti.

x86 register-register multiply mein IMUL kyun use hota hai, MUL kyun nahi?

MUL one-operand hai (implicitly EAX use karta hai, result EDX:EAX mein). IMUL ka two-operand form hai (IMUL EAX, EBX) jo do registers ko ek destination mein multiply karta hai.

Jab bahut saare intermediate values chahiye hote hain tab registers ki demand. Load/store architectures ko zyada registers chahiye kyunki saare computations registers se hone chahiye, memory se nahi.

Modern x86 CPUs micro-ops kyun use karte hain?

Woh complex x86 instructions ko simpler RISC-like micro-ops (load/store style) mein decode karte hain execution ke liye, better pipelining aur out-of-order execution paane ke liye.

RISC load/store ka instruction format kya hai?

Memory ops ke liye LOAD/STORE Rdest/Rsrc, [Rbase + offset]; ALU ops ke liye OP Rdest, Rsrc1, Rsrc2. Uniform formats faster decode enable karte hain.