RISC-V extensions (M, A, F, D, V, C): Question bank

5.1.8 · D5 · Hardware › Instruction Set Architecture (ISA) › RISC-V extensions (M, A, F, D, V, C)

Shuru karne se pehle, ek simple refresher taaki koi cheez undefined na rahe:

Definition Vocabulary jo tumhe chahiye hogi

Atomic ka matlab hai "har doosre core ke point of view se ek saath hota hai — koi doosra core half-finished state nahi dekh sakta."
Reservation ek chhota flag hai jo ek core raise karta hai yeh kehte hue "main is memory address ko dekh raha hoon; agar koi ise chhuye toh mujhe batao."
Signed vs unsigned bas yeh hai ki kya top bit ka matlab hai "yeh number negative hai" (signed) ya "yeh ek normal bada positive number hai" (unsigned).
Two's complement woh standard tarika hai jis se computers signed integers store karte hain: top bit ka negative weight hota hai. Ek 32-bit number ke liye value hai bits[30..0] normally count kiya minus bit[31] × 2³¹. Toh 0x80000000 ka matlab $- 2^{31}$ hai, aur addition/multiplication bilkul wahi circuits se kaam karta hai jaise unsigned — sirf top bits ki interpretation badlti hai.
Bias (floating-point mein) ek fixed number hai jo real exponent mein add kiya jaata hai taaki stored exponent hamesha ek plain non-negative count ho.

Neeche ke bit-level pictures multiplication, LR/SC, aur floating-point traps ko support karte hain — inhe kaam karte waqt dekho.

Pictures that power the traps

Ek product, do halves. Ek 32×32 multiply ek 64-bit result banata hai. MUL low half leta hai, MULH* usi product ka high half:

Figure — RISC-V extensions (M, A, F, D, V, C)

LR/SC retry loop. LR ek reservation raise karta hai; agar koi doosra core line likhta hai, SC fail ho jaata hai aur loop fresh data ke saath retry karta hai:

Float addition alignment. Mantissas ko add karne se pehle unhe ek shared exponent chahiye — chhote wale ko right shift karo:

IEEE-754 exponent map. Stored exponent field number line ko regions mein divide karta hai — zero/subnormal, normal, aur infinity/NaN:

Poori treatment ke liye 5.2.03-IEEE-754-floating-point dekho.

True or false — justify karo

Base ISA mein already integer multiply hai, isliye M extension sirf divide add karta hai.

False — plain base ISA (5.1.07-RISC-V-base-ISA) mein koi hardware multiply bhi nahi hai; M dono MUL* aur DIV* add karta hai. Ek base-only chip multiply ek shift-add software loop mein karta hai.

MUL aur MULH do independent multiplications compute karte hain.

False — ye ek full multiplication compute karte hain jiska product register se do-guna wide hota hai; MUL low half return karta hai, MULH usi product ka high half (do-halves figure dekho).

Agar tumhe sirf ek 32×32 product ke low 32 bits chahiye, toh operands ki signedness matter nahi karti.

True — two's-complement product ka low half bit-identical hota hai chahe inputs signed ya unsigned treat karein, isliye sirf ek MUL hai lekin teen MULH variants hain.

LR.W ke baad SC.W guarantee karta hai ki store succeed karega.

False — SC fail ho sakta hai (non-zero return kar sakta hai) agar kisi doosre core ne reserved line ko touch kiya, ya spuriously bhi; retry loop ka point yahi hai ki failure expected aur normal hai.

amoadd.w aur ek LR/SC loop jo add karta hai functionally interchangeable hain, isliye jo chaaho choose karo.

Mostly functionally true hai, lekin amoadd.w ek single instruction hai jo line ko directly lock karta hai, jabki LR/SC ek multi-instruction loop hai jo heavy contention mein livelock kar sakta hai — simple patterns ke liye AMO prefer karo.

A extension ko memory system ki koi help nahi chahiye; yeh purely ek CPU feature hai.

False — atomics cache coherence protocol pe ride karte hain. Reservation tab invalidate hota hai kyunki coherence already ek line ke writes broadcast karta hai.

F extension ke registers f0–f31 wahi registers hain jo integer x0–x31 hain.

False — F ek alag floating-point register file add karta hai. Tumhe explicitly FMV/load-store se data move karna padega; ye overlap nahi karte.

Source code mein jo bhi decimal likhte ho uski exact single-precision representation hoti hai.

False — sirf woh numbers jo mantissa width ke andar (integer)×2ᵏ ke roop mein express ho saken exact hain. 0.1 aur 0.2 binary mein forever repeat karte hain, isliye ye rounded store hote hain (dekho 5.2.03-IEEE-754-floating-point).

Double precision bas "single precision but slower" hai; number range same hai.

False — D ka 11-bit exponent (bias 1023) hai jabki F ka 8-bit (bias 127) hai, isliye range ≈±10³⁸ se ≈±10³⁰⁸ tak badhti hai, sirf precision nahi.

Ek chip RV32IMAC implement kar sakta hai jabki F aur D skip kar de.

True — extensions independently implementable hain. Float skip karne se FPU aur extra register file bach jaati hai; M, A, C parts F/D pe depend nahi karte.

Signed division DIV of MIN_INT by −1 ek exception raise karta hai, bilkul jaise x86 pe division by zero karta hai.

False — RISC-V mein koi divide traps nahi hain. MIN_INT ÷ −1 representable range overflow karta hai isliye yeh defined hai ki MIN_INT return kare (aur REM 0 return kare); koi fault nahi hota.

Spot the error

mulh t1, a0, a1 jahan a0, a1 do unsigned magnitudes hold karte hain — kya galat hai?

MULH dono operands ko sign-extend karta hai, isliye agar kisi ka top bit set hai toh use negative pad liya jaayega. Unsigned inputs ke liye MULHU use karo.

Ek programmer sc.w likhta hai bina pehle lr.w run kiye, ek plain conditional store expect karte hue.

SC ka matlab sirf ek prior LR reservation ke relative kuch hai; koi reservation raise na hone par yeh simply fail ho jaayega (ya contract ke hisaab se undefined behave karega). Yeh ek general "store-if" instruction nahi hai.

Ek LR/SC retry loop ke andar, koi lr.w aur sc.w ke beech ek unrelated address pe normal load/store insert karta hai.

Yeh dangerous hai — architecture sirf ek bahut chhote, restricted instruction sequence ke liye forward progress guarantee karta hai LR aur SC ke beech; stray memory accesses har baar reservation lose karwa sakte hain, ek infinite loop create karte hue.

Ek single-precision number ke liye true exponent −126 ko directly ek signed 8-bit field mein store karna.

Exponents biased store hote hain: tum −126 + 127 = 1 store karte ho, ek unsigned value. Raw signed exponents "magnitudes compare karne ke liye unsigned integer compare as bit patterns" wali trick tod denge.

Yeh claim karna ki 0x80000000 × 0x80000000 overflow karta hai aur represent nahi ho sakta.

Yeh bilkul fit hota hai: (−2³¹)² = 2⁶², jo 64-bit product mein aa jaata hai. MULH high half 0x40000000 return karta hai; kuch overflow nahi hota kyunki product width design ke hisaab se doubled hai.

Floating equality test karna if (0.1 + 0.2 == 0.3) se aur true expect karna.

Rounding ki wajah se 0.1 + 0.2 0.30000000000000004 banta hai; float comparisons mein tolerance use karo, kabhi exact == nahi.

Har DIV ko "hardware will fault, so I'll catch the exception" pattern mein wrap karke divide-by-zero handle karna.

Koi exception catch karne ko nahi hai — RISC-V defines karta hai ki DIV x, 0 all-ones (−1) return kare, DIVU x, 0 bhi all-ones, aur REM/REMU x, 0 dividend return kare. Agar tumhe error handling chahiye toh software mein divisor test karo divide karne se pehle.

Why questions

MULH teen flavours mein kyun aata hai (MULH, MULHU, MULHSU) lekin MUL ek hi kyun hai?

Product ka high half depend karta hai ki sign bits kaise interpret ki jaayein, isliye signed/unsigned/mixed alag top halves dete hain — jabki low half har interpretation ke liye identical hai, isliye ek MUL kaafi hai.

RISC-V ne divide-by-zero results ko trap karne ki jagah define karna kyun choose kiya?

Traps pipelines ko complicate karte hain aur exception machinery require karte hain; ek fixed return value define karne se division ek plain, side-effect-free instruction rehta hai aur software decide kar sakta hai check karna hai ya nahi — RISC-V ki minimalist philosophy match karte hue.

User mode mein lock kyun nahi bana sakte "critical section ke around interrupts disable karke"?

Interrupts disable karna ek privileged operation hai jo user code ke liye unavailable hai, aur yeh doosre core ko race karne se bhi nahi rokta. Atomics (A extension) multi-core race directly solve karte hain.

A extension cache coherence pe "piggyback" kyun karta hai instead of new hardware add karne ke?

MESI jaisi coherence protocols already har write ko ek cache line pe track aur broadcast karti hain, isliye reservation sirf us existing traffic ko sunti hai — koi naya signalling network nahi chahiye.

Floating-point exponent biased kyun store hota hai instead of signed two's-complement number ke?

Biasing bit pattern ko monotonic banata hai — do floats ki magnitudes compare karna unke bit patterns ka plain unsigned integer compare reduce ho jaata hai, jo hardware aur sorting exploit kar sakte hain.

0.1 + 0.2 == 0.3 ka result rounding mode pe kyun depend karta hai?

Har inexact operation current mode ke according round karta hai; default round-to-nearest-even 0.1+0.2 ko ...0004 tak round up karta hai, lekin round-toward-zero jaisa mode alag last bit pe land kar sakta hai — isliye "kaun se floats equal hain" mode-dependent hai.

F aur D ko ek "floating point" extension ki jagah do mein kyun split kiya?

Register width aur datapath ko 64 bits tak double karne mein real silicon area aur power lagti hai. Embedded audio/sensor chips ko aksar sirf single precision chahiye, isliye split karne se ye sirf utna pay kar sakte hain jitna use karte hain.

Hardware floating-point addition mein "align exponents" step ki zarurat hi kyun hai?

Tum sirf un mantissas ko add kar sakte ho jo same power of two represent karte hain; aligning chhote number ki mantissa ko right shift karta hai jab tak dono ek exponent share na karen, taaki bits place value ke hisaab se line up hon (alignment figure dekho).

Leading mantissa bit "implicit" (stored nahi) kyun hai normalized floats mein?

Ek normalized number hamesha 1.something × 2ᵏ hota hai, isliye leading 1 guaranteed hai aur use store karna ek bit waste karna hoga — ise drop karna ek extra bit of precision free mein deta hai.

Edge cases

SC kya return karta hai, aur success aur failure ke boundary pe uski value ka kya matlab hai?

Yeh rd mein 0 likhta hai success pe (store hua, atomicity hold ki) aur non-zero (typically 1) failure pe (reservation lost); zero being success bnez ko seedha retry pe branch karne deta hai.

Do cores dono ek LR/SC increment loop mein hamesha spin karte hain — kya progress guarantee hai?

Architecture sirf guarantee karta hai ki koi na koi core eventually succeed karega (system-wide forward progress) well-formed loops ke liye, yeh nahi ki koi particular core karega — ek core repeatedly haar sakta hai lekin counter hamesha advance karta hai.

RV32 pe DIV MIN_INT, −1 aur REM MIN_INT, −1 ka defined result kya hai?

DIV MIN_INT (0x80000000) return karta hai kyunki true quotient +2³¹ fit nahi hota, aur REM 0 return karta hai; dono specified hain, koi overflow flag ya trap nahi.

Reserved exponent fields: IEEE 754 mein all-zero aur all-ones exponents ka kya matlab hai?

All-zeros subnormals (aur ±0) encode karta hai, all-ones ±∞ aur NaN encode karta hai; ye exponent range se carved out hain (exponent-map figure dekho), isliye single precision ke usable exponents sirf −126…+127 tak run karte hain, full 8-bit span nahi.

Agar true product ko dono halves ki zarurat ho — MUL aur MULH se full value kaise reconstruct karte ho?

Full product high half register width ke barabar shift up plus low half ke barabar hai — yaani MULH MUL ke upar baithta hai jab tum dono words concatenate karte ho.

~10⁶ additions ke baad ek running single-precision sum ka kya hota hai numbers ke saath jo same magnitude ke around hain?

Har add 23 mantissa bits tak round karta hai, aur errors roughly total ka ek percent accumulate hote hain; accumulator ko double (52 bits) mein switch karna error ko kai orders of magnitude se kam karta hai chahe inputs single rahein.

Kya ek compressed-instruction (C) chip multiply bhi lack kar sakta hai?

Haan — C sirf existing instructions ko code density ke liye 16-bit forms mein re-encode karta hai (3.3.06-Instruction-encoding); yeh koi arithmetic capability add nahi karta, isliye M ke bina RV32C mein phir bhi koi hardware multiply nahi hai.

Kya MULHSU symmetric hai — kya tum swap kar sakte ho ki kaun sa operand signed hai?

Nahi. MULHSU rs1 ko signed aur rs2 ko unsigned fix karta hai; roles swap karne se interpretation badal jaati hai aur generally result bhi, isliye operand order yahan meaningful hai.

Recall Quick self-check

Product ka low half signedness-independent kyun hai? ::: Kyunki two's-complement addition/multiplication sign interpretation ki parwah kiye bina identical low bits produce karte hain — sirf high (sign-carrying) bits differ karte hain. Kaunsa flag atomics ko kaam karta hai, aur use kaun invalidate karta hai? ::: Per-core reservation flag, kisi bhi doosre core ke coherence write se reserved line par invalidate hota hai. Single precision ke liye bias 127 kyun? ::: Yeh $2^{8 - 1} - 1$ hai, exponent range ko centre karta hai aur exponents ko unsigned integers ke roop mein compare karne deta hai. RISC-V divide-by-zero par kya karta hai? ::: Kuch exceptional nahi — yeh ek defined value return karta hai (DIV ke liye −1, REM ke liye dividend); koi trap nahi, isliye software mein check karo.