CISC vs RISC philosophies — Hinglish notes

5.1.1 · Hardware › Instruction Set Architecture (ISA)

YEH debate exist hi kyun karti hai?

KYA cheez ne jawaab badal diya? Sasti memory + achhe compilers + yeh discovery ki fast simple hardware better pipeline karta hai.

EK HI task ko woh ALAG tarah kaise execute karte hain

Task: A = A + B jahan A, B memory mein hain.

Worked example CISC ka tarika

ADD [A], [B]      ; ek instruction: A padho, B padho, add karo, A mein likho

Yeh kyun kaam karta hai: hardware/microcode internally loads, add, aur store karta hai. Code ki ek line, ek memory-heavy instruction jo kaafi cycles leti hai.

Worked example RISC ka tarika

LOAD  R1, [A]     ; Kyun? RISC ADD mein memory operands forbid karta hai
LOAD  R2, [B]     ; Kyun? B ko bhi ek register mein le aao
ADD   R3, R1, R2  ; Kyun? arithmetic sirf registers par — fast, uniform
STORE [A], R3     ; Kyun? sirf STORE memory mein likhta hai

Yeh kyun kaam karta hai: zyada instructions hain, lekin har ek simple, fixed-length hai, aur cleanly pipeline karti hai. Compiler ki zimmedaari hai inhe arrange karna.

Core trade-off, first principles se derive kiya hua

Worked example Numbers se concrete hota hai

Program do taaron se run kiya. Maano clock cycle time normalized hai.

	$N$	CPI	rel. $T_{c}$	CPU time
CISC	1.0M	4.0	1.25	$1.0 \times 4.0 \times 1.25 = 5.0$
RISC	1.5M	1.1	1.0	$1.5 \times 1.1 \times 1.0 = 1.65$

RISC yahan kyun jeetta hai: woh 50% zyada instructions use karta hai, phir bhi total time bahut kam hai kyunki CPI aur cycle time dono shrink ho gaye. Ek table mein pura RISC argument yahi hai.

Modern plot twist

Common mistake Galat ideas ko steel-man karna

Galat idea 1: "RISC faster hai kyunki iske paas kam instructions hain." Kyun sahi lagta hai: naam hai "Reduced." Fix: RISC programs mein usually zyada instructions hote hain ( $N$ bada). "Reduced" matlab hai ki har instruction simpler hai, programs chhote nahi. Speed aati hai low CPI + short cycle time + pipelining se, instruction count se nahi.

Galat idea 2: "CISC instructions hamesha kam cycles leti hain." Kyun sahi lagta hai: ek CISC line kaafi RISC lines replace karti hai. Fix: ek CISC instruction internally bahut saare cycles le sakti hai (high CPI), toh total cycles necessarily kam nahi hote.

Galat idea 3: "RISC matlab complex instructions kabhi exist nahi karti." Kyun sahi lagta hai: "reduced." Fix: RISC-V/ARM mein multiply, vector, crypto extensions hain. Rule yeh hai ki load/store separation + fixed encoding, na ki useful ops ko "ban" karna.

Galat idea 4: "Modern x86 pure CISC hai." Fix: woh internally μops mein decode hota hai — hybrid hai.

Galat idea 5: "Har RISC ISA mein kam se kam 32 registers hote hain." Kyun sahi lagta hai: MIPS/RISC-V/ARMv8 sab 32 expose karte hain. Fix: yeh ek common design goal hai, rule nahi — classic 32-bit ARM mein sirf 16 integer registers hain phir bhi woh poori tarah RISC hai. Defining traits hain load/store separation + fixed-length encoding, koi magic register count nahi.

Recall Feynman: ek 12-saal ke bachche ko samjhao

Socho LEGO se banana. CISC aise hai jaise kuch giant pre-built pieces hon — ek poora car door ek piece mein. Ek pakadna fast hai, lekin special pieces ka dabba bhaari hai aur unhe banane wali factory complicated hai. RISC aise hai jaise sirf tiny basic bricks hon. Usi door ke liye tumhe zyada bricks aur clear instructions chahiye, lekin bricks saste hain, super fast snap hote hain, aur tum kuch bhi bana sakte ho. Clever baat yeh hai: ek achhe instruction sheet (compiler) ke saath, bahut saari tiny bricks actually thodi giant lumpy ones se tezi se banati hain.

Forecast-then-Verify

Flashcards

CISC aur RISC kis sawaal ke alag-alag jawaab dete hain?

Complexity kahaan rahni chahiye — hardware mein (CISC) ya software/compiler mein (RISC).

RISC mein kaun si instructions memory access kar sakti hain?

Sirf LOAD aur STORE (load/store architecture); saari arithmetic register-to-register hoti hai.

Kya RISC mein "Reduced" ka matlab hai program mein kam instructions?

Nahi — usually program mein ZYADA instructions hoti hain; har instruction simpler hoti hai.

CPU time equation do.

CPU Time = N × CPI × T_c (instruction count × cycles per instruction × cycle time).

RISC larger N ke bawajood faster kyun ho sakta hai?

Kyunki woh CPI ko 1 ki taraf drive karta hai aur simple hardwired control + deep pipelining ke zariye cycle time chota karta hai, aur yeh gains higher N se zyada dominant hain.

Microcode kya hai aur kaun sa style isko rely karta hai?

Ek internal layer jo ek complex instruction ko micro-ops mein expand karti hai; classic CISC isko rely karta hai.

Modern x86 CPUs dono ko kaise blend karte hain?

Woh CISC instructions ko RISC-jaisi micro-ops (μops) mein decode karte hain jo ek RISC-style core par execute hoti hain.

Typical instruction length: CISC vs RISC?

CISC = variable length (x86: 1–15 bytes); RISC = fixed length (jaise 32-bit).

Fixed-length encoding RISC ki help kyun karta hai?

Instruction fetch/decode uniform aur predictable hoti hai, jisse pipelining simpler aur faster hoti hai.

Ek CISC ISA aur ek RISC ISA ka naam bolo.

CISC: x86 / VAX / 68k. RISC: ARM / MIPS / RISC-V.

Kya saare RISC ISAs mein ≥32 registers hote hain?

Nahi — yeh ek common goal hai (MIPS/RISC-V/ARMv8 mein 32 hain) lekin classic 32-bit ARM mein sirf 16 hain; defining traits hain load/store + fixed-length encoding.

CISC historically kyun aaya?

Mehengi/scarce memory + haath se likhi assembly ne dense, zyada kaam karne wali instructions ko prefer kiya.

Connections

Pipelining — RISC ka fixed-length, single-cycle design hi woh cheez hai jo clean pipelines possible banata hai.
Microcode and Micro-operations — woh mechanism jo CISC internally use karta hai aur x86 RISC-jaisa kaise banta hai.
CPU Performance Equation — N × CPI × Tc framework jis par yeh poora trade-off tikaa hai.
Addressing Modes — CISC ke rich modes vs RISC ka minimal set.
Compiler Optimization — RISC jaanbujhkar complexity yahaan shift karta hai.
x86 vs ARM — is debate ka modern real-world instance.
Instruction Encoding — fixed vs variable length formats.