Place and route (P&R)

4.2.5 · Hardware › VLSI Design

WHAT is P&R?

WHY it matters: Modern chips mein, wires — gates nahi — delay, power, aur area par dominate karte hain. Ek logically-correct netlist tab tak useless hai jab tak use legally (koi overlap nahi, koi design-rule violations nahi) aur well (timing/power meet kare) place aur route na kiya jaaye. Yahan "logic" "physics" banta hai.

The inputs and outputs

STEP 1 — Placement (the WHY of good placement)

Goal: total wirelength minimize karo jabki cells legal rakhein (non-overlapping, on-grid, timing/density meet karte hue).

Why wirelength is the key objective

Wire delay length ke saath badhta hai, aur wire capacitance $\propto$ length, isliye: $P_{\text{dyn}}=\alpha C{V}^{2}f,C\propto \text{wirelength}$ Shorter wires $\Rightarrow$ less $C\Rightarrow$ less delay aur less dynamic power. Isliye wirelength minimize karna sab kuch optimize karne ka ek proxy hai.

HOW we estimate wirelength: Half-Perimeter Wirelength (HPWL)

Placement is done in phases

1. Global placement — coarse positions jo $\sum$HPWL minimize kare (thoda overlap allow karta hai; analytic/quadratic optimization se solve hota hai).
2. Legalization — cells ko rows/sites par snap karo, minimal movement ke saath overlaps hatao.
3. Detailed placement — remaining wirelength squeeze karne ke liye small local swaps.

STEP 2 — Routing

Goal: har net ko metal layers + vias use karke physically connect karo, design rules (min spacing/width) ka paalan karte hue, no shorts/opens ke saath.

Why layered routing (Manhattan style)

Routing phases

1. Global routing — chip ko GCells ke ek grid mein divide karta hai; decide karta hai ki har net kaunse coarse regions se guzregi, congestion (demand vs. track capacity) balance karte hue.
2. Detailed routing — har region ke andar exact tracks, wires, aur vias assign karta hai, design-rule violations (DRC) fix karta hai.

Timing closure (why P&R iterates)

Placement wire length affect karta hai → wire delay → clock constraint meet hogi ya nahi: $t_{\text{arrival}}=t_{\text{gate}}+t_{\text{wire}}\le T_{\text{clk}}-t_{\text{setup}}$ Agar routing ke baad koi path bahut slow hai, to tool us path ko re-place / re-route / buffer karta hai. P&R ek iterative optimization loop hai, ek baar mein khatam nahi hota.

Common mistakes

Active recall

Flashcards

Connections

• Logic Synthesis — wo netlist produce karta hai jo P&R consume karta hai.
• Floorplanning — placement se pehle chip outline/macros define karta hai.
• Static Timing Analysis (STA) — check karta hai ki placed+routed paths $T_{clk}$ meet karti hain ya nahi.
• Clock Tree Synthesis (CTS) — placement aur routing ke beech insert hota hai.
• Design Rule Checking (DRC) — routed geometry validate karta hai.
• Interconnect delay / RC model — kyun wirelength delay se map hoti hai.
• Standard Cell Library — physical + timing data jo P&R drive karta hai.

Concept Map