Standard cell libraries — Hinglish notes

4.2.4 · Hardware › VLSI Design

Intuition The big picture (WHY these exist)

Socho ek ghar banana hai. Tum khud har ek brick, hinge, aur window frame — raw clay aur metal se — mould kar sakte ho — total control, lekin isme ek lifetime lag jaati. Uski jagah tum pre-made, pre-tested standardized parts khareedte ho (fixed size ki bricks, fixed height ke doors) aur sirf unhe assemble karte ho. Ek standard cell library chip design ke liye exactly wahi hai: ek catalogue of pre-designed, pre-characterized, pre-verified logic building blocks (INV, NAND, NOR, DFF...) jinki fixed cell height hoti hai, taaki tool unhe automatically neat rows mein snap kar sake. WHY it matters: yeh "billions of transistors haath se design karna" ko "library cells ek menu se place karna" mein badal deta hai, jisse automated synthesis and place-and-route possible hoti hai.

What is a standard cell?

The multiple "views" of one cell

Ek single cell jaise NAND2_X2 kaafi coordinated views ke saath ship hoti hai:

View	What it contains	Used by
Liberty (`.lib`)	timing, power, capacitance	synthesis, STA
LEF	abstract footprint: pins, blockages, size	place & route
GDSII	full mask-level layout (transistors, metal)	fabrication
Verilog	functional model (`assign Y = ~(A&B)`)	simulation
SPICE netlist	transistor-level	characterization

Why a FIXED cell height? (The core trick)

Height tracks mein measure hoti hai — horizontal routing tracks ki wo number jo fit hoti hain. Ek "9-track" library "7-track" se taller (faster, zyada area) hoti hai (denser, lower power).

Characterization: where the numbers come from

Formula Cell delay model (derive it)

WHAT: humein ek number chahiye, propagation delay $t_{p d}$ , situation ke function ke roop mein. WHY it depends on load: ek gate ek switch hai jo ek capacitor $C_{L}$ drive karta hai. Output flip karne ke liye use charge $Q = C_{L} \cdot V$ dump/remove karna padta hai. Transistor se current limited hai, toh bada load → zyada time.

Output transition ko ek RC charge ki tarah model karo: $V_{o u t} (t) = V_{D D} (1 - e^{- t / (R_{o n} C_{L})})$ 50 % reach karne ka time solve karo: $0.5 = 1 - e^{- t_{p d} / (R_{o n} C_{L})} \Rightarrow e^{- t_{p d} / (R_{o n} C_{L})} = 0.5$ $t_{p d} = R_{o n} C_{L} ln 2 \approx 0.69 R_{o n} C_{L}$

Real cells mein input slew (kitni fast input edge hai) par bhi dependence add hoti hai, toh .lib ek 2-D table store karti hai: $t_{p d} = f (input slew, C_{L})$ aur interpolate karti hai. Isse NLDM (Non-Linear Delay Model) kehte hain.

PVT corners

Drive strength aur $V_{t}$ flavours (the 80/20 knobs)

Worked examples

Common mistakes (steel-manned)

Active recall

Recall Quick self-test (answers chupaao)

Sabhi cells ek fixed height kyun share karti hain? → taaki rows tile hon aur power rails abut hon, automated P&R enable ho.
Drive strength X4 vs X1 mein do kya changes hote hain? → lower $R_{o n}$ (faster) lekin higher input cap aur leakage.
NLDM delay table mein kaun se do variables index karte hain? → input slew aur output load capacitance.
$t_{p d}$ constant derive karo. → $0.5 = 1 - e^{- t / R C} \Rightarrow t = R C ln 2 \approx 0.69 R C$ .
Router kaun sa view use karta hai? → LEF. Fab? → GDSII.

Recall Feynman: ek 12-saal ke bachche ko explain karo

Chip banana LEGO se banana jaisa hai. Khud har tiny piece carve karne ki jagah, LEGO tumhe standard bricks ka ek box deta hai jo sab click together hote hain kyunki woh same height ke hain. Standard cell library wahi LEGO box hai: chote logic bricks (AND, NOT, memory bits) jinki sabki same height hai, taaki ek robot unhe neat rows mein snap kar sake aur "electricity wires" automatically line up ho jayein. Kuch bricks "strong, fast" wali hoti hain (badi, zyada power leti hain) aur kuch "slow, energy-saving." Engineers har brick ke liye ek cheat sheet rakhte hain jo batata hai woh kitni fast hai aur kitna power use karti hai, taaki computer best mix choose kar sake.

Connections

Static Timing Analysis — .lib NLDM delay tables consume karta hai.
Logic Synthesis — RTL ko library cells par map karta hai, drive strength aur $V_{t}$ choose karta hai.
Place and Route — cells ko rows mein tile karne ke liye LEF footprints use karta hai.
CMOS Inverter — $t_{p d} = 0.69 R_{o n} C_{L}$ model yahin se aata hai.
Power Dissipation in CMOS — $V_{t}$ flavours ke peeche leakage vs speed trade-off.
Technology Nodes — ek library ek node se tied hoti hai (7 nm, 28 nm...).

What is a standard cell?

Ek pre-designed, pre-characterized logic/storage element jisme fixed height, fixed-position power rails, aur known timing/power/area models hote hain.

Why do standard cells have a fixed height?

Taaki woh rows mein tile hon aur unki VDD/VSS rails abut hon, automated row-based place-and-route enable ho sake.

Name four views shipped for one cell.

Liberty (.lib) timing/power, LEF footprint, GDSII layout, Verilog/SPICE functional model.

Which view does the router use vs the fab?

Router LEF use karta hai (abstract); fab GDSII use karta hai (full mask layout).

Derive the 0.69 factor in cell delay.

Vout=VDD(1-e^{-t/RC}) se, 50% set karo: 0.5=1-e^{-t/RC} ⇒ t=RC·ln2 ≈ 0.69RC.

What two variables index an NLDM delay table?

Input transition (slew) aur output load capacitance.

What does drive strength X4 vs X1 change?

~4× wider transistors ⇒ ~1/4 Ron (faster) lekin ~4× input capacitance aur higher leakage/area.

LVT vs HVT trade-off?

Low-Vt = fast lekin leaky (critical paths); High-Vt = slow lekin low-leakage (baaki jagah).

What is a PVT corner?

Ek Process/Voltage/Temperature combination jis par cells characterized hoti hain (jaise slow-slow, high-T, low-V worst case).

Why is a delay table used instead of one formula?

Transistor behaviour nonlinear hai; SPICE ko slew×load grid par sample karke interpolate karna zyada accurate hai.

What defines a "track" library (7T vs 9T)?

Routing tracks mein cell height; zyada tracks = taller = faster lekin bada area.